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Design Languages >> Verilog-AMS >> concatenate bits into bus in Verilog-A
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Message started by ssdfz on Nov 3^rd, 2008, 7:52pm

Title: concatenate bits into bus in Verilog-A
Post by ssdfz on Nov 3^rd, 2008, 7:52pm

Hi everyone:

I created a 5-bit adder in Verilog-A, and when I tried to instantiate the 5-bit adder, FA_5bit, in a larger verilog-A system, I run into the following problem:
FA_5bit i2 (.A(IN[2:0]), .B({ J, K, H }), .CO(CO), .S(S[2:0]), .CI(CI)); HSPICE complains about the concatenation symble "{" saying "syntax error"
The simulation would otherwise go through I change the code as the following:
FA_5bit i2 (.A(IN_SUB[2:0]), .B(IN_SUB[2:0]), .CO(CO), .S(S[2:0]), CI(CI));

Could someone points me where I was wrong?

Many thanks
Erik

Title: Re: concatenate bits into bus in Verilog-A
Post by patrick on Nov 3^rd, 2008, 10:03pm

This Verilog-A feature is not supported in the current HSPICE release (0809). However it is available in the next major release (0903).

Patrick

Title: Re: concatenate bits into bus in Verilog-A
Post by ssdfz on Nov 4^th, 2008, 8:37pm

Thanks Patrick.

So before the new release, is there any work around? Or I have to split the 3-bit FA into single bit adder adder and connect them together?

Thanks