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Design Languages >> Verilog-AMS >> Hierarchically referece a node in verilog-A instantiation
https://designers-guide.org/forum/YaBB.pl?num=1225859737

Message started by ssdfz on Nov 4^th, 2008, 8:35pm

Title: Hierarchically referece a node in verilog-A instantiation
Post by ssdfz on Nov 4^th, 2008, 8:35pm

Hi all:
I have a question regarding getting access to hierarchical node in VA and hope it can be answered by experts in this forum. For example, I need to get access to two nodes called global.vdd and global.vss. In Verilog-HDL, I simply create a module called global and their net can be hierarchically referred. I tried the similar thing in verilog-A, but it seems to fail.
One example would be that if I need to instantiate the following VA model
module test(A, Z);
input A;
output Z;
electrical A;
electrical Z;

electrical B;

test1 i0 (.A(B), .Z(B));
test2 i1 (.A(B),.B(global.vss), .Z(Z));
endmodule

I tried to write a separate global.va model which is having vss, and include the file in my hspice input file, but no luck.

Your opinion will be highly appreciated!

Title: Re: Hierarchically referece a node in verilog-A instantiation
Post by jbdavid on Nov 4^th, 2008, 9:44pm

that is not something that ALL the Verilog-A simulators support.
What happens in many simulators with the Spice (or spectre) netlist on top is that you need to put those ports Explicitly in the model, and then connect them to global nets in the spice netlist.

jbd