The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> DAC nonliear problem?
https://designers-guide.org/forum/YaBB.pl?num=1225868870

Message started by chiarella on Nov 4^th, 2008, 11:07pm

Title: DAC nonliear problem?
Post by chiarella on Nov 4^th, 2008, 11:07pm

Dear all:

DAC nonliear problem is found in my chip which is a 8 bits SAR DAC using the resistor ladder. I run the simulation again, but it works well.

anybody knows why this error happens in my DAC?

Title: Re: DAC nonliear problem?
Post by vivkr on Nov 5^th, 2008, 2:29am

Hi,

What nonidealities do you include in your simulation? And what sort of simulation are you running?

I don't know the exact design details, but you seem to have the classic nonlinearity in your SAR DAC which comes from element mismatch. Have you assumed a reasonable level of mismatch in your calculations/simulations?

Regards,
Vivek

Title: Re: DAC nonliear problem?
Post by chiarella on Nov 5^th, 2008, 4:26pm

Hi,

the op-amp's offset, resistor ladder's mismatch is considered, but I don't think it is the reason for nonliearity.
Actually this DAC is very simple resistor ladder structure, firstly I also think the reason is device's mismatching.
I run the transient analysis, the reason is very good steps.

do you have any idea about this nonliearity? which element will cause this error? Actually if it is current steering DAC, I think nonliearity is more easy to happen, but now it is resistor ladder. I have no idea.

Title: Re: DAC nonliear problem?
Post by vivkr on Nov 5^th, 2008, 11:37pm

Hi,

Mismatch is equally likely to happen in a resistor ladder as in a current-steering DAC. Apart from random mismatch which you can reduce with large sized resistors, and excellent common-centroid layout with dummies, there will also be systematic mismatch which you will see if your layout is not good.

Have you measured several parts? Do you see the same nonlinearity profile (more or less) for all of them? If yes, then your layout is to blame. If you see random profiles for nonlinearity, then it is residual mismatch, to reduce which you would need to make the resistors larger.

I suspect you have layout issues. Measure nonlinearity for 20-30 parts and then compare the profiles.

Regards,
Vivek

Title: Re: DAC nonliear problem?
Post by chiarella on Nov 6^th, 2008, 1:35am

thanks , vivkr

today I found the problem. the reason is the MOSFET switch. two kinds of MOSFET is used as a switch, Pmos is used to conduct the voltage higher than half of the Maximum voltage, Nmos is used for lower.
When test engineer use the probe to measure the DAC output, the drop voltage of MOSFET is generated. When the input is changing from 127 to 128, the switch also changed from PMOS to NMOS, so the equivalent resistor is different, so the drop voltage is different.

I hope you can understand my explaination.

thanks again.

Title: Re: DAC nonliear problem?
Post by rf-design on Dec 15^th, 2008, 2:39pm

I think you use a PMOS to NMOS divided ladder tap switch because the ladder spans from VDD to VSS.

If the application makes only capacitive load the seetling time will also a little bit different but the DC-effect vanish.

Was there a reason not to use complementary switches? The the ladder you be universal connected.