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Design Languages >> Verilog-AMS >> modelling using verilog -ams
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Message started by mtech84 on Nov 5^th, 2008, 4:08am

Title: modelling using verilog -ams
Post by mtech84 on Nov 5^th, 2008, 4:08am

hi all,

is it necessary to know verilog-a , verilog and system verilog completely to run verilog ams.

Title: Re: modelling using verilog -ams
Post by Geoffrey_Coram on Nov 5^th, 2008, 5:09am

No.

There's probably no one who understands all of System Verilog -- even the experts have debates about what the language really allows or doesn't. :)

Title: Re: modelling using verilog -ams
Post by mtech84 on Nov 10^th, 2008, 10:59pm

another query , if I only have schematic design build using analoglib so is it possible to simulate only the design with the cadence ams simulator, i mean creating the test bench of the design and then config and choosing the ams template....... and so on ......

Title: Re: modelling using verilog -ams
Post by Geoffrey_Coram on Nov 11^th, 2008, 4:34am

I don't understand what you are asking. Are you asking if one can simulate a design made exclusively of components from analoglib in AMS Designer? I would think so -- I don't think you have to have a V-AMS component to use AMS Designer.

But I don't use the config/hierarchy editor myself.