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Simulators >> RF Simulators >> KT/C noise with Pnoise analysis
https://designers-guide.org/forum/YaBB.pl?num=1226068552

Message started by Ziolizzi on Nov 7^th, 2008, 6:35am

Title: KT/C noise with Pnoise analysis
Post by Ziolizzi on Nov 7^th, 2008, 6:35am

Hi everybody,

this is my first message, I'm a new member.

Let me explain my problem with the Pnoise analysis.
I tried to simulate a very simple S/H circuit in order to plot the KT/C noise at the output node. In the following you can see the netlist file I used:

simulator lang=spectre
global 0
parameters VDD=1.8
include "/cds/technologies/umc_018_2008/designkit/UMC_18_CMOS/../Models/Spectre/MM180_SPECTRE_MAIN_V142.lib.scs" section=tt
include "/cds/technologies/umc_018_2008/designkit/UMC_18_CMOS/../Models/Spectre/MM180_SPECTRE_MAIN_V142.lib.scs" section=diode
include "/cds/technologies/umc_018_2008/designkit/UMC_18_CMOS/../Models/Spectre/MM180_SPECTRE_MAIN_V142.lib.scs" section=bjt
include "/cds/technologies/umc_018_2008/designkit/UMC_18_CMOS/../Models/Spectre/MM180_SPECTRE_MAIN_V142.lib.scs" section=res_typ
include "/cds/technologies/umc_018_2008/designkit/UMC_18_CMOS/../Models/Spectre/MM180_SPECTRE_MAIN_V142.lib.scs" section=mimcaps_typ
include "/cds/technologies/umc_018_2008/designkit/UMC_18_CMOS/../Models/Spectre/MM180_SPECTRE_MAIN_V153.lib.scs" section=tt
include "/cds/technologies/umc_018_2008/designkit/UMC_18_CMOS/../Models/Spectre/018-rf-v2d4-control.scs"
include "/cds/technologies/umc_018_2008/designkit/UMC_18_CMOS/../Models/Spectre/MM180_RES_V111.lib.scs" section=res_typ

// Library name: prova
// Cell name: prova_noise_RF
// View name: schematic
V2 (net7 VCM) vsource dc=0 type=dc pacmag=1
I10 (SOUT 0 OUT 0) SH_IDEAL
M0 (net7 P2 OUT _net0) p_18_mm w=10u l=180.0n ad=4.9e-12 as=4.9e-12 \
pd=20.98u ps=20.98u m=(1)*(1)
M24 (net7 P1 OUT 0) n_18_mm w=10u l=180.0n ad=4.9e-12 as=4.9e-12 pd=20.98u \
ps=20.98u m=(1)*(1)
C0 (OUT VCM) capacitor c=10p ic=0
V0 (VCM 0) vsource dc=VDD/2 type=dc
V3 (_net0 0) vsource dc=VDD type=dc
V5 (P2 0) vsource type=pulse val0=VDD val1=0 period=2.5u delay=0 rise=1n \
fall=1n width=1u
V7 (P1 0) vsource type=pulse val0=0 val1=VDD period=2.5u delay=0 rise=1n \
fall=1n width=1u
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output" checklimitdest=psf
pss pss fund=400K harms=0 errpreset=conservative tstab=16.6u
+ saveinit=yes tstabmethod=gear2only maxacfreq=6M
pnoise ( OUT 0 ) pnoise start=0.001 stop=4M dec=200
+ maxsideband=5 iprobe=V2 refsideband=0 annotate=status
+ saveallsidebands=yes
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
ahdl_include "/home/pasquale/cad18_v2/prova/SH_IDEAL/veriloga/veriloga.va"

As you can see the circuit is very simple, furthermore I downloaded the SH_IDEAL verilogA model directly from this site.

The simulation settings are the same of the file "Simulating Switched-Capacitor Filters with SpectreRF" (Listing1).
At the end of the simulations, if I try to plot the output PDS the result is very different from Figure4 (in the same document).
I really don't understand where the problem is..

Do you have any suggestion?

Thank you for your support.

Ziolizzi

Title: Re: KT/C noise with Pnoise analysis
Post by Andrew Beckett on Jan 3^rd, 2009, 3:15pm

Isn't it just because you have a higher clock frequency, and the results plotted on a log x-axis (the paper has them on a linear x-axis).

Regards,

Andrew.