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Design >> Mixed-Signal Design >> DAC Testing, worst case input bit pattern for maesurement of SFDR in DAC
https://designers-guide.org/forum/YaBB.pl?num=1226174318

Message started by Mahavir on Nov 8^th, 2008, 11:58am

Title: DAC Testing, worst case input bit pattern for maesurement of SFDR in DAC
Post by Mahavir on Nov 8^th, 2008, 11:58am

Hello Friends,
I need your help.......

I am working on BIST of Digital to Analog Converters and I need to generate a signal on-chip to measure SFDR and SINAD ratio of DAC.
Generally SFDR of DAC is defined with assuming input as digital bit pattern for monotonic sine wave. But I want to know which signal will prove to be worst case input for DAC such that a DAC giving reasonable SFDR for that signal will always be considered to work for other type of input bit-patterns.
Also plz tell me are there any other methods to calculate SFDR except the conventional frequency spectrum and FFT calculation based one?

Thanks in Advance

Title: Re: DAC Testing, worst case input bit pattern for maesurement of SFDR in DAC
Post by Peruzzi on Nov 8^th, 2008, 12:46pm

Mahavir,

What kind of DAC is it? How many bits? Weighted or equal elements?

Do you have an on-chip ADC? How many bits?

I can think of a few possibilities, depending on what's in there.

- Bob Peruzzi

Title: Re: DAC Testing, worst case input bit pattern for maesurement of SFDR in DAC
Post by Mahavir on Nov 8^th, 2008, 1:01pm

Well, I am supposed to design the BIST architecture assuming the DAC to be a black box. It will be a 8-bit DAC. Once the BIST for DAC is designed I wish to extend it further to sort of correcting error incurred.
The application I am planning to go for is communication DAC. I am also not very sure about what difference the architecture will make on the BIST. Through literature survey I found that generally hey prefer testing for static parameters than dynamic ones like SFDR and SNR

Title: Re: DAC Testing, worst case input bit pattern for maesurement of SFDR in DAC
Post by rf-design on Dec 15^th, 2008, 2:50pm

The device yield coverage is very good for DAC's with static values. That is because there are no functional caps.

In worst case you have to step linear trough all values. If the architecture is segmented you test a number of MSB bits in the linear mode and the remaining LSB bits with leading rolling 1 or 0. The should give some hundred BIST gates.

Title: Re: DAC Testing, worst case input bit pattern for maesurement of SFDR in DAC
Post by ywguo on Dec 17^th, 2008, 8:39am

Hi,

I would like to integrate a DDFS with the DAC. DDFS can generate a sinusoidal signal. The DAC output is fed to a spectrum analyzer for measuring SFDR. As well known, the SFDR is related to DNL/INL in fact. Furthurmore, SFDR is important for a communication DAC. Right?
Sure it is not feasible if the DAC output is NOT available outside the chip.
Any literature on BIST for DAC, please share it with us.

Yawei