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Design >> Mixed-Signal Design >> Process insenstitive delay cell
https://designers-guide.org/forum/YaBB.pl?num=1226416950

Message started by smarty on Nov 11^th, 2008, 7:22am

Title: Process insenstitive delay cell
Post by smarty on Nov 11^th, 2008, 7:22am

Hi all,
I wanted to have a process insensitive delay cell. Is there any way we can achieve this. I tried with current starved inverter and thought of controlling the delay with current, but I am unable to achieve delay insensitive to process variation or minimal variation with process.
Can anybody suggest, whether we can achieve the delay insensitive to process variation, if so whether I can get anything in literature.

Thanks and Regards,
SBR

Title: Re: Process insenstitive delay cell
Post by Berti on Nov 12^th, 2008, 12:56am

Sure, a delay-locked loop (DLL) can be design to serve as a process-independent
delay-line.

Cheers

Title: Re: Process insenstitive delay cell
Post by smarty on Nov 12^th, 2008, 1:02am

Thanks Berti.
I know this should sound a bit vague, but in any way can we control the delay of a cell over PVT if the delay cell is operate in open loop?.

Thanks and Regards,
SBR

Title: Re: Process insenstitive delay cell
Post by Berti on Nov 12^th, 2008, 7:09am

I don't know.
At least the temperature dependence can probably be reduces when using a PTAT
current.

Cheers

Title: Re: Process insenstitive delay cell
Post by smarty on Nov 12^th, 2008, 7:36am

Thanks Berti...

What I thought was (quite possible I might be wrong also) by using a controlled delay element, like current controlled delay element or VCDL(voltage controlled delay cell), we could achieve reducing the process variation of the delay.
Do you have any thought regarding this.

Thanks and Regards,
SBR

Title: Re: Process insenstitive delay cell
Post by Berti on Nov 13^th, 2008, 6:08am

Sure, but the generation of the control-current (or voltage) that compensates the delay variation will be the real challenge.

Cheers

Title: Re: Process insenstitive delay cell
Post by smarty on Nov 13^th, 2008, 7:42am

Thanks Berti.. I am finding hard as you suggested in generating the control.
With your experience can you suggest any trick by which we can get the control work as needed.

Thanks,
SBR

Title: Re: Process insenstitive delay cell
Post by fonseca.ha on Nov 16^th, 2008, 9:31am

Hi. What is the aplication?

A very accurate way to delay signals by a controled ammount is having a master DLL that generates a control voltage.

After that, the control voltage can be used on a "Slave" delay line in open loop.

A simplier way is if the DLL is digital but you may end up with more jitter.

Another way could with the following:
Using the Band Gap Voltage and a Switched Capacitor Resistor To generate a current.
After use that current (I) to charge a capacitor. The ramp I/C depends only on the ratio of capacitors! so it can be quite accurate!

Alternativelly
Do you have access to a well defined reference current. Perhaps by using an external resistor?

Cheers,
H

Title: Re: Process insenstitive delay cell
Post by loose-electron on Dec 5^th, 2008, 1:56pm

This has been done many times with a PLL or DLL - You have two delay paths, one in the PLL/DLL and the other in the delay path that you are trying to control.

the two delay blocks sit close to each other (same process/temperature conditions) and connect to the same power (same power voltage conditions)

The delay of both the PLL/DLL and the Delay Path are under control of the PLL/DLL feedback system. The PLL/DLL is connected to a reference clock and set to get the desired VCO(PLL) or Delay Line (DLL) time delay needed.

The control voltage tracks out the PVT effects, and you are done.

-- Jerry

Title: Re: Process insenstitive delay cell
Post by neoflash on May 6^th, 2009, 10:48am

I guess Mr. Smarty is looking for a design which generate a delay like 1ns without using any know reference clock frequency or reference of timing delay.

And he wished to have small variation from process skew and voltage/temperature change.

Right?

Title: Re: Process insenstitive delay cell
Post by smarty on May 31^st, 2009, 8:27am

All,
Sorry for not able to reply in advance as I was away and had not checked this.

But yes what Mr. Neoflash is saying is to an extent correct. I was trying to generate a delay for which I do not have any reference clock with minimal PV variation.

Thanks,
SBR