The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> A confusion in PSS simulation https://designers-guide.org/forum/YaBB.pl?num=1226492332 Message started by subgold on Nov 12th, 2008, 4:18am |
Title: A confusion in PSS simulation Post by subgold on Nov 12th, 2008, 4:18am A switched capacitor system has different behavior (e.g. small-signal or noise) in different clock phases, because the operating points are changing periodically. So what exactly does the pss simulation tell us? We run a pss+pxf and get one transfer function, but there should be different transfer functions for each periodic state. For instance, how to simulate the small-signal gain of an amplifier which uses a typical switched capacitor CMFB? Since the amplifier only properly operates in one clock phase (the amplifier is disconnected from the CMFB in the other phase), the results acquired from pss represent which phase? How to obtain the information only from the amplification phase? I think I am confused with the basic principle of the pss simulation. Hope somebody could help, thanks in advance. |
Title: Re: A confusion in PSS simulation Post by Frank Wiedmann on Nov 12th, 2008, 6:00am See http://www.designers-guide.org/Analysis/sc-filters.pdf. |
Title: Re: A confusion in PSS simulation Post by Tlaloc on Nov 12th, 2008, 8:47am subgold wrote on Nov 12th, 2008, 4:18am:
Don't confuse the individual states that the amp will be in from the discrete time transfer function. Take the example of an simple integrator. During the sample time, the amp just holds its previous value and is disconnected from the input, i.e. H=0. During the transfer phase, it looks just like a standard amplifier, i.e. H=Cs/Ci (sample cap/integrate cap). However, from the charge equations the 'real' discrete time transfer function is H=Cs/Ci*1/(1+z-1). That is very different from the individual state transfer functions, which are useless in and of themselves. The PSS and all of the other P-analyzes return information about the combined discrete time equations. Quote:
That's not true since the hold caps are still in the circuit. Even a SC CMFB must maintain some type of negative feedback through all phases of operation. Quote:
You will most likely need to use an ideal track and hold that is discussed in Frank's reference. Quote:
Another thread with the same question: http://www.designers-guide.org/Forum/YaBB.pl?num=1223636443 |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |