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Design Languages >> Verilog-AMS >> how to model a vccap?
https://designers-guide.org/forum/YaBB.pl?num=1227597419

Message started by ricky on Nov 24^th, 2008, 11:16pm

Title: how to model a vccap?
Post by ricky on Nov 24^th, 2008, 11:16pm

hello,everyone
I am a beginner of verilog-a.I am working on a CDC(cap to digital converter).i need to model a vccap. this is my code:
module c_module(c_p,c_n,vp,vn);
inout c_p ,c_n,vp ,vn;
electrical c_p,c_n,vp,vn;
parameter c0=1.0;
real c;
analog begin
c=c0*V(vp,vn);
I(c_p,c_n)<+c*ddt(V(c_p,c_n));
end
endmodule

but error found by spectre as follows:
an operand dependent on the output of a dot() operator (dynamic expression) can not be used in a multiplication opeeration when the other operand is dependent on a probe or the simulation time.
consider using a node to hold the dynamic expression and probe this node in the multiplication operation.

thanks for your help!
ricky

Title: Re: how to model a vccap?
Post by Geoffrey_Coram on Nov 25^th, 2008, 3:43am

This has been covered already in this forum (and elsewhere), but it's faster to fix your code than to find the reference:

analog begin
I(c_p,c_n) <+ c0 * ddt( V(vp,vn) * V(c_p,c_n) );
end

The current is ddt of the charge, q=CV; since both V's depend on time, you need both inside the ddt.

Title: Re: how to model a vccap?
Post by Frank Wiedmann on Nov 25^th, 2008, 4:14am

The reference is http://www.designers-guide.org/Modeling/varactors.pdf.

Title: Re: how to model a vccap?
Post by ricky on Nov 25^th, 2008, 6:32am

thanks a lot!

Title: Re: how to model a vccap?
Post by ricky on Nov 25^th, 2008, 7:18pm

hi Geoffrey_Coram,
i think that i made a mistake in my describing. :-[
my vccap is a four teminals device,and (vp vn) is a control signal which is irrelevant to (v_p,v_n).
i can find a four teminals vccap model in CADENCE analogLib,but sadly i find this model cannt be set any CDFparameter. why about this?
please forgive me for my trivial question and thank you for any help.
ricky

Title: Re: how to model a vccap?
Post by Peruzzi on Nov 26^th, 2008, 6:12am

Ricky,

Begin by describing the vccap mathematically. Don't worry about modeling language yet. What is the capacitance between vp and vn as a function of the voltage on the control inputs?

From there on it's easy: Look up the correct syntax for cap = f(controls), then write the differential equation for the current through vp to vn as a function of the voltage across vp and vn.

CAVEAT: Avoid any mathematical step on the control voltage or you will run into convergence difficulties. That's easy too. If you own the model which drives the control voltage, drive the control voltages with the transition() function in that model. If not, there are several other ways to avoid the infinite slope of a step in your vccap model. (Read Ken K's book!)

Best regards,

Bob P.

Title: Re: how to model a vccap?
Post by Peruzzi on Nov 26^th, 2008, 6:25am

Ricky,

On second thought, don't worry about voltage steps on the control inputs. It would be better to use transition() on the capacitance evaluation, to avoid any mathematical steps of the capacitance.

Bob P.