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Design >> Mixed-Signal Design >> how to finish such a by-4 divider without reset
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Message started by trashbox on Nov 26^th, 2008, 5:28am

Title: how to finish such a by-4 divider without reset
Post by trashbox on Nov 26^th, 2008, 5:28am

I need to divide a clock(freq=200KHz, duty cycle is 40~60%) by 4 without reset signal. This clock is IN at the attachment and the desired output is OUT at the attachment.

Many counter need a RESET control signal. If no RESET is available, How can I realize such a function? Thanks!

Best regards
Trashbox

Title: Re: how to finish such a by-4 divider without reset
Post by Berti on Nov 26^th, 2008, 10:20pm

You could write a short VHDL/Verilog.

Otherwise you can also use a simple ripple counter (flip-flops with feedback) and combine input, divide-by-2 and divide-by-4 with logic to generate the desired duty-cycle. Finally you still can synchronize the clock to the input.

Cheers

Title: Re: how to finish such a by-4 divider without reset
Post by aamar on Nov 27^th, 2008, 1:13am

A 4 bit shift register with a constant input HIGH and comparing the first 3 bits using an AND3, the 4th stage recieves the high signal which is the reset for all the stages including itself. A delay stage (inverters) has to be inserted between the output of the 4th stage and the resets otherwise it could come to instability.

B0-B1-B2-Reset-Output
0 - 0 - 0 - 0 0 <---------------------------
1 - 0 - 0 - 0 0 |
1 - 1 - 0 - 0 0 |
1 - 1 - 1 - 0 1 |
1 - 1 - 1 - 1 --> Delay < clock_period/2 0 - 0 -0 - 0

Best regards,

aamar

Title: Re: how to finish such a by-4 divider without reset
Post by ywguo on Dec 1^st, 2008, 10:40pm

Hi Trashbox,

Although most counters have a RESET signal input, I think they can operate w/o any RESET signal input except that the counter has a dead state. A dead state is that a Finite State Machine will not reach the desired state when it is a dead state. For eg., a simple counter 00->01->11->10->00 ... has not any dead state.

Yawei

Title: Re: how to finish such a by-4 divider without reset
Post by Tlaloc on Jan 27^th, 2009, 6:49pm

The only problem with tying the reset pin to ground is simulation. If you are trying to run this in verilog, you will always get X at the output. In real life, however, the flops will start at one of the four states in an indeterminate manner, but the output is well behaved so long as you don't care about the initial condition.