The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Simple adder - help!!
https://designers-guide.org/forum/YaBB.pl?num=1227809194

Message started by vabian on Nov 27^th, 2008, 10:06am

Title: Simple adder - help!!
Post by vabian on Nov 27^th, 2008, 10:06am

Sorry, but my English is not good.
I have a problem with a adder. Hery is a code and a result of simulation (in cver):

module sumator_bez(a,b,wykonaj,wynik);
input [3:0] a,b;
input wykonaj;

output [3:0] wynik;
reg [3:0] wynik;

always @(wykonaj) begin
if(a[3:0] > b[3:0])
begin
wynik = a - b
end
else
begin
wynik = b - a;
end
end

initial begin
#130 $finish;
end

endmodule

module test;
reg [3:0] a,b;
reg wykonaj;
wire [3:0] wynik;

sumator_bez S (a,b,wykonaj,wynik);

initial begin
a = 10; b = 5; wykonaj = 1;
#50 a = 7; b = 5; wykonaj = 1;
#50 a = 3; b = 4; wykonaj = 1;
end

initial begin
$monitor($time, ": %d - %d = %d",a,b,wynik);
end
endmodule

Simulation:
Highest level modules:
test

0: 10 - 5 = 5
50: 7 - 5 = 5
100: 3 - 4 = 5
Halted at location **mod.v(27) time 130 from call to $finish.
There were 0 error(s), 0 warning(s), and 4 inform(s).

Why did the result of a-b don't change?

When I change instuction wynik=a-b on assign wynik=a-b I get a new result of simulation. But if-else don't work properly. Why?
Highest level modules:
test

0: 10 - 5 = 5
50: 7 - 5 = 2
100: 3 - 4 = 15

Thanks for any help!!!

Title: Re: Simple adder - help!!
Post by Ken Kundert on Nov 27^th, 2008, 10:55am

You only recompute the output upon changes in wykonaj, but that signal never changes.

-Ken

Title: Re: Simple adder - help!!
Post by vabian on Nov 27^th, 2008, 12:24pm

Ken Kundert wrote on Nov 27^th, 2008, 10:55am:

You only recompute the output upon changes in wykonaj, but that signal never changes.

-Ken

Could you tell me, what I should to change in my code? I will weveryy great full

Title: Re: Simple adder - help!!
Post by Ken Kundert on Nov 27^th, 2008, 10:46pm

Use "always @(*) begin" rather than "always @(wykonaj) begin".

-Ken