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Simulators >> Circuit Simulators >> Monte Carlo Analysis
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Message started by nxing on Dec 4^th, 2008, 11:08am

Title: Monte Carlo Analysis
Post by nxing on Dec 4^th, 2008, 11:08am

Hello everybody,

I have a general quesiton regarding the Monte Carlo analysis with Cadence application + TSMC 65n technology model file. When you run MC analysis with "process&Mismatch", will the simulator randomly pick up any cornor, then run mismatch at that particular cornor or will it run
some process and some mismatch (for example, 40 run for process and 60 runs for mismatch if you have a total 100 runs) analysis and then combine the data?

Thanks

N.X.

Title: Re: Monte Carlo Analysis
Post by ywguo on Dec 8^th, 2008, 12:49am

Hi nxing,

I have not TSMC 65n SPICE model. However, I have TSMC 0.18um SPICE model which support Monte Carlo analysis. That is a BSIM 4.5 model. I guess the 65nm SPICE model is similar.

If you run MC analysis with "process&Mismatch", the simulator does not pick any corner. The TSMC SPICE model assigns random values to those model parameters. I guess the random values meet a normal distribution. Perhaps TSMC's engineers think that distribution covers all corner variation and mismatch. Actually it results in a over pessimistic design.

Yawei

Title: Re: Monte Carlo Analysis
Post by Andrew Beckett on Jan 8^th, 2009, 5:23am

Each parameter which is varied will have two distributions, one for process, and one for mismatch. For each parameter, it will compute a random value using the process distribution for each point in the monte carlo. This is then effectively the mean about which the mismatch variation is then computed for each device in the circuit (for that monte carlo point).

So process and mismatch are computed for all points in the monte carlo.

Normally (at least this should be the goal), the statistical variation of the parameters should reflect a more realistic coverage of the process+mismatch distribution, and may never actually include the corners. I would say that corners-based design tends to lead to overly pessimistic (or overly cautious) design, because the corners are statistically very unlikely to occur - whereas if you look at the yield over all your monte carlo runs, you're going to get a more realistic picture. Note it doesn't mean that you need to get all points in the monte carlo simulation to meet the spec, but that you get a sufficient yield. If you use corners, you don't have much choice other than making sure all the corners meet the spec, because you don't know how close they are to failing, and so on.

In addition it's possible to have regions of failure which aren't covered by corner models.

That said, all of this is dependent on how good the statistical and corner models actually are!

Regards,

Andrew.

Title: Re: Monte Carlo Analysis
Post by Tlaloc on Jan 27^th, 2009, 3:06pm

I also have not run TSMC 65n but have run TSMC 0.18um. In the model files there, both local and process variations are gaussian, however, I have seen other processes that use the uniform distribution for process variations. The rational for this is that a number of lots separated by only a little time may appear to be gaussian, however, there can be some major shift in the fabrication process that looks almost like a step function. This could be from anything like using a different stepper or getting a new lot of the same process recipe except from a different physical fab. Because these shifts tend to affect a number of wafers closely separated by time, if a design is marginal close to a corner, you could experience a large yield hit due to that shift.

Having said all of that, I agree with Andrew about the corners being statistically unlikely, but taking the practical nature of processing into account, you want to make sure that skewed lots still meet your design parameters.

What I typically do is only run mismatch in my monte carlo, and repeat the MC runs through the different corners. That way I am guaranteeing that mismatches at the extremes do not break the design.

Title: Re: Monte Carlo Analysis
Post by vikas_memory on Aug 3^rd, 2009, 3:20pm

@Tlaloc, how do you intend to specify the corners? Is it by assigning sigma values to parameters or by specifying the exact location in the global variation?

I am running MC on 6t SRAM bit cell using Hspice and am stuck at the local variation. I am not able to specify the exact point at which it must do mismatch. For example, the worst case static noise margin was found to be 160mV from the Hspice output listing. Is there a way to tell Hspice to do mismatch variations around this point?