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Design >> Analog Design >> reference buffer specs. for ADC ?
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Message started by Ajay on Dec 6^th, 2008, 6:26am

Title: reference buffer specs. for ADC ?
Post by Ajay on Dec 6^th, 2008, 6:26am

I have a technical question:
I need to design a reference buffer for a successive approximation ADC. This ADC uses a capacitive DAC array. What is the procedure to determine the reference buffer specifications such as gain , bandwidth, gain margin etc. ??
Is there a document outlining this or can you suggest any set of simulations to determine the above requirements ?
I will greatly appreciate your kind response.

Title: Re: reference buffer specs. for ADC ?
Post by rf-design on Dec 15^th, 2008, 1:41pm

The settling time of the reference will be the most important. The switches rearanging the caps would be not be limiting the settling time. Design your reference buffer with a close to Q=sqrt(0.5) damping. The loop bandwidth "including" the approximation load cap define the settling time. If the supply of the buffer have some 10nH inductance to outside and some 100pF internal buffering, your first sims should include them. So he should provide good rejection.