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Modeling >> Behavioral Models >> Model for Average current consumption in Verilog
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Message started by Sinner on Dec 10^th, 2008, 4:54am

Title: Model for Average current consumption in Verilog
Post by Sinner on Dec 10^th, 2008, 4:54am

Hi,

I am relatively new to verilog
Anyone has a model for current measurement for PMC. For both peak currents and average currents.

Title: Re: Model for Average current consumption in Verilog
Post by jbdavid on Dec 18^th, 2008, 11:44am

This has been here a while with no answers..
in Verilog-A we usually measure current with an

Code:

Imeas = I(node1,node2);

statement.. but "PMC" to me should be followed with "Sierra" - probably not what you meant.. care to expound?

Title: Re: Model for Average current consumption in Verilog
Post by Sinner on Dec 18^th, 2008, 8:30pm

Thanks..

In this case it stands for Power management controller
:)

I am using this construct, to elaborate

I have to measure the current flowing from the supply to my PMC with the supply itself ramping up or down.

Using

I(n1,n2) <+ V(n1,n2)*1/r where r is a very low value resistance to minimize the drop

gives me extremely high current values

Is their another way to do this measurement?

Title: Re: Model for Average current consumption in Verilog
Post by rajdeep on Dec 19^th, 2008, 3:32am

Hi,

Are you adding the small r to measure the current?

If that is the case you do not need that perhaps!
Just use, var = I(pwrp,pwrp_PMC) to probe
the current thru pwrp, pwrp_PMC branch.
Make sure that these two nodes are shorted to each other
in your design. I assumed pwrp = the node that corrsponds
to the power supply and pwrp_PMC = node that is connected
to the power supply pwrp. var is a real variable.

This should help.

Rajdeep

Title: Re: Model for Average current consumption in Verilog
Post by Sinner on Dec 23^rd, 2008, 3:38am

Thanks Rajdeep,

I found another way to do it.

I have shorted my PAD and PMC Supply and in parallel I am using a CCCS with gain of 1, so whatever current flows in the branch also flows from the dependent source.

Title: Re: Model for Average current consumption in Verilog
Post by rajdeep on Dec 24^th, 2008, 3:07am

Thats great!

Just one point here. My suggestion of using var = I(pwrp,pwrp_PMC)
can be looked as a current controlled variable! So, instead of var,
if you use an electrical branch, say I(p,n) then it becomes your CCCS!
But, whatever way you right, the most imp thing was to short pwrp, pwrp_PMC before probing the current thru that branch :), which
you have done now!

Rajdeep