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Design >> Analog Design >> CMFB sensing circuit
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Message started by adesign on Dec 10^th, 2008, 10:02pm

Title: CMFB sensing circuit
Post by adesign on Dec 10^th, 2008, 10:02pm

Hi,

I've come across an opamp for an integrator of a sigma-delta ADC. The figure given
in this mail shows the CMFB sensing circuit for this opamp.

In the attached figure, OUTP and OUTM are the differntial output nodes of the
opamp. phi1 is the integrating phase and phi2 is the sampling phase. phi1 and
phi2 are two non-overlapping clocks operating at around oversampling ratio of
128. CMFB is the output common-mode voltage sensed by this circuit.

My queries are:
1) How is this CMFB sensing circuit working?
2) For doing ac analysis of the opamp, what load should be connected at the
opamp outputs? There is no tranac(ac simulation at some transient point) option
in my simulator.

Please comment.

Regards,
ADesign

Title: Re: CMFB sensing circuit
Post by ricky on Dec 25^th, 2008, 5:56pm

Hi,ADesign
i face the same question as you when using a sc CMFB for an integrator of a sdadc...do you get a solution?

Title: Re: CMFB sensing circuit
Post by loose-electron on Dec 25^th, 2008, 6:29pm

You need to show the sequence of the clock signals for this to be meaningful. It looks like you are doing capacitive voltage averaging, but without the clocking sequence it is tough to say.

Title: Re: CMFB sensing circuit
Post by adesign on Dec 28^th, 2008, 11:57pm

The clocking sequence is attached herewith.

Title: Re: CMFB sensing circuit
Post by thechopper on Dec 29^th, 2008, 4:08am

Hi ADesign,

The circuit you are using is averaging the differential outputs of your amplifier, so that such voltage is afterwards amplified and fed back by means of your CMFB circuit.
Just think of each switched capacitor as if it was a resistor: in average it behaves as such. When you replace it by a resistor you are left with a resistive network and the capacitors connected in parallel provide a zero for compensating some other pole in the CMFB loop.

Hope this helps
Tosei

Title: Re: CMFB sensing circuit
Post by aaron_do on Dec 29^th, 2008, 7:29am

Hi,

I'm not sure exactly how it works...are you sure you drew it correctly? I'm not too sure about switched cap circuits anyway, so maybe its right...

Anyway i just wanted to add that its probably feeding back the average of 2VC - (OUTP+OUTM) ... i.e. the error signal...I'd be interested in how VC comes into the picture though.

cheers,
Aaron

Title: Re: CMFB sensing circuit
Post by adesign on Dec 29^th, 2008, 8:16pm

Hello Aaron,

Thanks for your reply. VC is the desired output common mode voltage generated from some reference bias.

-ADesign

Title: Re: CMFB sensing circuit
Post by adesign on Dec 29^th, 2008, 8:20pm

Thanks Tosei.

What is the purpose of R here? Is it current limiting resistor when the output swing is maximum?

This condition may arise when the output swing is maximum.

Title: Re: CMFB sensing circuit
Post by aaron_do on Dec 30^th, 2008, 1:14am

Hi,

I understand that VC is the desired common-mode voltage, but i'm a bit puzzled how it actually fits in. When you write VC above the wire, is that supposed to be a voltage source , VC, accross the cap?

Also a bit unsure why you need R when the switched cap is supposed to emulate a resistor...

cheers,
Aaron

Title: Re: CMFB sensing circuit
Post by adesign on Dec 30^th, 2008, 1:27am

Hi,

Yes, VC is the voltage source.

I think R is to limit the current when OUTP and OUTM are at +/-maxima. Please correct me, if I'm wrong.

Thanks,
ADesign

Title: Re: CMFB sensing circuit
Post by thechopper on Dec 30^th, 2008, 2:42pm

Hi ADesign,

I think the series R could be there to just provide a pole in your CMFB loop. Such pole might be there for stability reasons and/or for providing antialiasing means for your CMFB circuit. I do not think the second option makes too much sense though, since usually noise aliasing in a CMFB circuit is not relevant.

Regards
Tosei

Title: Re: CMFB sensing circuit
Post by XY-oriented on Jan 5^th, 2009, 2:08am

hi guys...
I don´t thing the schematic is correct because VC don't play any role … but if the left PH2 switches are connect to GND instead of VC such that C1 is charged with a voltage of -VC then when PH1 is active averaging occur in each half branch (assuming C1=C2)
((VOUTP-VCMFB)-VC)/2 + ((VOUTM-VCMFB)-VC)/2
and VCMFB=(VOUTP+VOUTM)/2 -VC as expected

is my analysis right ? What do you think ?

Title: Re: CMFB sensing circuit
Post by aaron_do on Jan 5^th, 2009, 3:21am

Quote:

but if the left PH2 switches are connect to GND instead of VC such that C1 is charged with a voltage of -VC

that's what i was thinking too...

Title: Re: CMFB sensing circuit
Post by thechopper on Jan 6^th, 2009, 6:39pm

Hi XY-oriented,

I think your analysis is correct, except that instead of GND you should connect the left PHI2 swtich to the desired voltage to bias any current source inside the opamp topology.

Such voltage difference (current source bias - VC) is the one performing the comparison in the SC CMFB circuit.
Ultimately what the circui shhould give at CMFB node is

VCMFB=(VOUTP+VOUTM)/2 -(VC-current source bias)

I think the posted circuit just shows the sensing part of the CMFB but it is not complete since the comparsion is missing.

Regards
Tosei

Title: Re: CMFB sensing circuit
Post by XY-oriented on Jan 6^th, 2009, 11:46pm

Thanks Tosei,
you are right ... I forgot the bias ;)

Redouane

Title: Re: CMFB sensing circuit
Post by Tlaloc on Jan 27^th, 2009, 12:48pm

The left and right sides of the P2 switches set the input and output common mode (relative to this block), respectively. Let the voltage at the left branch be VCM1 and the other VCM2, then the charge equations come out to be the following.

(VOUTP+VOUTM)/2-VCM1=VCMFB-VCM2

There are times that the circuit as shown is useful if the desired voltage is VC, but as Tosei mentioned, the majority of times, VCM2 is a bias voltage for current mirrors.

As far as the resistors, I've never seen them used before, but I would have to agree with Tosei that they are for some extra pole.