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Design Languages >> Verilog-AMS >> AMS simulation run time
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Message started by k_arkal on Dec 18^th, 2008, 9:47pm

Title: AMS simulation run time
Post by k_arkal on Dec 18^th, 2008, 9:47pm

I'm running verilog AMS on a very simple verilog A model of an A to D converter. It took me about one and a half hours to 1.5 seconds of simulation time.
I'm wondering if this is this the nomal speed I can expect or is there any parameter I need to control.
I'm running my job on a very high end machine. Using spectre with turbo option and liberal option.
Thanks,
-KA

Title: Re: AMS simulation run time
Post by jbdavid on Dec 18^th, 2008, 11:36pm

If that's ALL that's in your simulation, I doubt the turbo option helps.
I'm running a simple receiver and am only a 120us after over a week..
Make the ADC model mixed signal so that the CLOCK and digital output pins in the ADC never touch the spectre solver.. it will probably run a LOT LOT faster..
(especially if the clock rate is higher than the analog signal bandwidth you are sampling.. and it should be a LEAST 2x..
remember that the clock results in a MINIMUM of 4 timesteps per cycle if it goes to analog side.. point are at the start and stop of each transition..

(THIS is the one of the fatal (to me) flaws of SpectreVerilog simulator..) your using AMS.. only half of that ADC is analog..
jbd

Title: Re: AMS simulation run time
Post by k_arkal on Dec 19^th, 2008, 2:04pm

Hello,
I'm not clear when you say
"Make the ADC model mixed signal so that the CLOCK and digital output pins in the ADC never touch the spectre solver.."

can you please elaborate on this?
Thanks a lot for your help.
k_arkal

Title: Re: AMS simulation run time
Post by rajdeep on Dec 19^th, 2008, 3:53pm

Spectre is not very efficient in handling discrete events. The digital simulators are more efficient in this regard. So, in a mixed signal design it is better to model the discrete events such as clocking using
the digital (Verilog-D) constructs of Verilog-AMS. This will ensure that spectre does NOT try to solve ('touch') the discrete events (as you have modeled them using Verilog-D constructs), rather the digital simulator will do that in a more efficient way and the overall run-time could be significantly less!!
[By Verilog-D I mean the usual Verilog language used for logic signals e.g. always]

Title: Re: AMS simulation run time
Post by k_arkal on Dec 19^th, 2008, 4:04pm

Hi,
In my simulation I'm using a Voltage source from the analogLib for clock. Instead of using the voltage source, if I used a verilog-D construct to define my clock, teh simulation might run faster?

Thansk you very much,
-k_arkal.

Title: Re: AMS simulation run time
Post by rajdeep on Dec 22^nd, 2008, 2:04am

Never tried! But seems unlikely as those are primitive blocks and spectre probably has better way (predefined) way of handling them. But if your clock has enabling feature then it makes sense to code
it in verilog as your simulation will be very fast when the clock is not ticking (disabled). But a primitive voltage pulse from analogLib will tick always.

Hope it helps!
Rajdeep

Title: Re: AMS simulation run time
Post by sheldon on Jan 2^nd, 2009, 7:59am

KA,

I think that Jonathan was referring to using a different style
of modeling based on real number modeling. One reference
that may help is the following,

http://www.bmas-conf.org/2002/papers/bmas02-david.pdf

Best Regards,

Sheldon