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Design >> Mixed-Signal Design >> Regulator design for ADCs from accuracy perspective
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Message started by spanandiyer1979 on Dec 24^th, 2008, 7:54am

Title: Regulator design for ADCs from accuracy perspective
Post by spanandiyer1979 on Dec 24^th, 2008, 7:54am

Hi Guys

I want to design a regulator for an ADC. It takes a 1.2 V reference from a Bandgap and outputs 1.8V which is the ADC supply.Now the ADC imposes accuracy requirements on the regulator output : less than 0.4mV change in the Regulator output of 1.8V when the ADC is switching(=0.02%). 0.4mV is half the LSB for ADC. So please let me know how to go about a regulator design with such accuracy requirements.
The usual regulator designs I have found have accuracies of the order of 1%.

Anand

Title: Re: Regulator design for ADCs from accuracy perspective
Post by sheldon on Dec 25^th, 2008, 6:35am

Anand,

How did you calculate the regulator load regulation requirement?

Best Regards,

Sheldon

Title: Re: Regulator design for ADCs from accuracy perspective
Post by spanandiyer1979 on Dec 29^th, 2008, 12:32pm

Hi Sheldon

Can you please clarify ? Well the specific requirement came from ADC. The supply to the ADC(1.8V) comes from the regulator. The ADC requires that when it is switching the impact on the supply be less than 0.4mV. I dont think this is load regulation strictly.
Anyways if you can point me out some regulator specifically for ADC supply it would be great help.
Thanks
Anand

Title: Re: Regulator design for ADCs from accuracy perspective
Post by sheldon on Dec 30^th, 2008, 4:25am

Anand,

Your calculation seems to assume that the ADC has no intrinsic
rejection. Hence the question, "How did you budget the supply
rejection?" In addition, is it really reasonable to require the reference
to reject the switching transients? This will require a very wide
bandwidth reference. Wouldn't it be better to use on-chip bypassing
to provide the high frequency rejection? One other comment, the
ADC package inductance is going to make it difficult to meet this
specification.

Best Regards,

Sheldon

Title: Re: Regulator design for ADCs from accuracy perspective
Post by spanandiyer1979 on Dec 30^th, 2008, 9:07am

Hi Sheldon

I am not designing the ADC. I got the requirements. However the ADC is not differential. And It is a SAR ADC.So can you please comment on the ADC intrinsic rejection ?
Also I am also having the same doubt if it is at all reasonable to require the reference to reject transients to *such* an extent. Well if I do put an off chip external cap(as is done in usual LDOs) then I see that the switching transients are really small(less than 0.4mV). So I dont see why the reference of the gain bandwidth has to be any larger than say, 50 MHz.
Also can you please elaborate on the ADC package inductance? FYI, both the regulator and ADC will be on the same chip.
The thing is if I see the ADC datasheets they depict the supply design to be an ideal voltage source with bypass caps to filter out the noise. What I am doing is putting an on chip regulator which will go to the ADC supply. I am not sure whether I am missing something here since I am not into ADC design at all and this is the first time I am designing a regulator.
Any pointers would be of help!
Anand