The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> frequency trimming in crystal for RTC(Real-time clock) https://designers-guide.org/forum/YaBB.pl?num=1230209158 Message started by trashbox on Dec 25th, 2008, 4:45am

Title: frequency trimming in crystal for RTC(Real-time clock) Post by trashbox on Dec 25th, 2008, 4:45am Hi all, Regards to the 32.768KHz crystall oscillation circuit design for Real-time clock(RTC), some papers use tuning capacitors for frequency trimming such as the red capacitor Cx in the attachment. However, 32.768KHz crystal generally has a very small motional capacitor(Cs=2f~5f farad) and load capacitors C1 and C2 are about 10p~20p.So that the nominal frequency is mostly determined by Cs and Ls, which means if I want to tune frequency from 32.764Khz to 32.768Khz, I have to add about 8p farad as Cx. Is this trimming technology reasonable or popular for crystal design for RTC? How can I get a precise 32.768Khz nominal frequency for RTC? Thanks in advance! Regards, Trashbox

Title: Re: frequency trimming in crystal for RTC(Real-time clock) Post by loose-electron on Dec 25th, 2008, 6:45pm Frequency pulling like this is a bit iffy. 1. The simple single inverter oscillator structure in CMOS is a very inefficient structure. As an example, to get sufficient gain over corners, the geometry needs to be pushed up in size quite a bit. It's an I/O cell so it ends up being pretty big as it is.) That geometry increase causes a huge variance in static DC current. Over PVT corners in 45nm TSMC CMOS and 2db of open loop gain margin the current varies from about 80uA to  12mA - Huge! 2. Frequency pulling of a crystal, is stongly dependent on the Q of the crystal. You may want to look at the extremes of the stand alone crystal accuracy, and the requirements of your real time clock. The structure as illustrated reduces the gain of the loop and not much else. 3. What comes out of a crystal is a sinusoid, without harmonic content. The pulling circuit shown will largely just reduce the sinusoind amplitude. Need a low Q to work well, and most crystals are 10E4 to 10e5 in Q. There are some papers out there on crystal pulling, need to do some research there.

Title: Re: frequency trimming in crystal for RTC(Real-time clock) Post by trashbox on Dec 31st, 2008, 5:04pm Hi loose-electron! Thanks for your comments! Regards, Trashbox loose-electron wrote on Dec 25th, 2008, 6:45pm: Frequency pulling like this is a bit iffy. 1. The simple single inverter oscillator structure in CMOS is a very inefficient structure. As an example, to get sufficient gain over corners, the geometry needs to be pushed up in size quite a bit. It's an I/O cell so it ends up being pretty big as it is.) That geometry increase causes a huge variance in static DC current. Over PVT corners in 45nm TSMC CMOS and 2db of open loop gain margin the current varies from about 80uA to  12mA - Huge! 2. Frequency pulling of a crystal, is stongly dependent on the Q of the crystal. You may want to look at the extremes of the stand alone crystal accuracy, and the requirements of your real time clock. The structure as illustrated reduces the gain of the loop and not much else. 3. What comes out of a crystal is a sinusoid, without harmonic content. The pulling circuit shown will largely just reduce the sinusoind amplitude. Need a low Q to work well, and most crystals are 10E4 to 10e5 in Q. There are some papers out there on crystal pulling, need to do some research there.

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