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The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> SC-CMFB clock issue https://designers-guide.org/forum/YaBB.pl?num=1231486519 Message started by seahs on Jan 8th, 2009, 11:35pm |
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Title: SC-CMFB clock issue Post by seahs on Jan 8th, 2009, 11:35pm I am trying to use sc-cmfb in a fully differential OTA, which is going to be used in double-sampled flip-around differential SHA. I am wondering the relation between clocks of the sc-cmfb and clocks of the SHA. should the clocks of the sc-cmfb be much higher than clocks of the SHA.? |
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Title: Re: SC-CMFB clock issue Post by Berti on Jan 9th, 2009, 4:03am Probably it is not a good idea to switch the CMBF during the output of the SHA settles. I would therefore recommend to use the same clock frequency and arrange the CMFB clock-phases in a way to balance the capacitive load of the SHA. Cheers |
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Title: Re: SC-CMFB clock issue Post by thechopper on Jan 10th, 2009, 8:48am I would probably use the same clock frequency, and sample the common mode signal when sampling the input signal, while transfering the common mode charge when the SH output is updated. Regards Tosei |
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Title: Re: SC-CMFB clock issue Post by neoflash on Feb 12th, 2009, 7:28am I'm having difficulty to understand SC-CMFB. Except for the steady-state results of final settling relationship of output common mode, I can't imagine how the circuit works continuously. Any recommendation for reading more than "Analysis of switched-capacitor common-mode feedback circuit"? |
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Title: Re: SC-CMFB clock issue Post by neoflash on Feb 12th, 2009, 7:33am HdrChopper wrote on Jan 10th, 2009, 8:48am:
Such slow update rate of the CMFB holding capcitors is adequate? How to analyze this circuit CMFB instead of simulation? |
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Title: Re: SC-CMFB clock issue Post by thechopper on Feb 15th, 2009, 6:27pm I guess it will depend on whether the amplifier is "active" on both clock phases of your circuit or not. I'm assuming you are talking about a standard SC-CMFB. If not, could you post a schematic of such circuit. Regards Tosei |
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Title: Re: SC-CMFB clock issue Post by subgold on Feb 16th, 2009, 2:37am neoflash wrote on Feb 12th, 2009, 7:33am:
it removes the CM error by integration over several clock cycles. I don't think it is very slow. How fast do you expect it to be? |
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Title: Re: SC-CMFB clock issue Post by neoflash on Feb 16th, 2009, 3:57am subgold wrote on Feb 16th, 2009, 2:37am:
The update rate is supposed to be much higher than CM signal changing rate. Since CM signal's change is not supposed to be huge, due to the high-CMRR of the fully differential opamp, I guess refresh the capacitor once per integration cycle is adquate, right? |
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Title: Re: SC-CMFB clock issue Post by neoflash on Feb 16th, 2009, 4:04am HdrChopper wrote on Feb 15th, 2009, 6:27pm:
The amplifier is active on both clock cycles. I love the idea of doing the CMFB refreshing at integration cycle. However, I've seen a design doing the CMFB refreshing at input sampling cycle. I'm curious whether this CMFB refreshing cycle could be reversed at will? |
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Title: Re: SC-CMFB clock issue Post by Berti on Feb 16th, 2009, 8:35am Hi Neoflash, It doesn't matter in which phase you refresh the CMFB. But usually it is done during the sampling phase in order to balance the capacitive load of the amplifier. I am not sure if I understand that right, but to my understanding is the speed (bandwidth) of the SC-CMFB independent of the clock frequency. Regards |
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Title: Re: SC-CMFB clock issue Post by neoflash on Feb 17th, 2009, 7:01am Berti wrote on Feb 16th, 2009, 8:35am:
I did an experiment and find that if I do CMFB refresh in sampling phase, then in integrating phase the output Common mode voltage is not well regulated. Instead, the CM voltage during sampling phase is very well controlled. However, I don't think the CM voltage in sampling phase is important. At this phase, OPAMP is not supposed to process signal. I prefered to do the CMFB cap refreshing at integration phase, and let output CM in integration phase to be regulated. Right? |
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