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Design Languages >> Verilog-AMS >> cross statement
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Message started by nishant22 on Jan 19^th, 2009, 1:50am

Title: cross statement
Post by nishant22 on Jan 19^th, 2009, 1:50am

Hi,
I have a big code for transmitter and have various cross statements which contribute to slowing down simulation speed considerably. Can anyone suggest like if my events are dependent on the rising or falling edge of the clock where vth= vdda(1)+vssa(0)/2 i write it as @cross(V(clk) -vth, 1) how can i replace the cross statements in my block with may be something better.
Thanks in advance
Nishant

Title: Re: cross statement
Post by rajdeep on Jan 21^st, 2009, 6:02am

Hi Nishant,

cross statements are used to enusure the simulator does not miss the all important events, like for your example positive edge of a clock. You may need to add tighter tolerances sometimes so that a numerical simulator like spectre doesnt miss it.

So, if you do not want to use cross, then you are taking a risk and your model is becoming less robust!!

But from my own experience sometimes you can remove some of the cross statements if you are sure that the simulator is anyway going to take time steps small enough to NOT miss the event.

I can suggest 3 ways:

1. For your clock example, consider clk is the signal name, and th = (vdd+vss)/2, be the threshold.
Then,....

analog begin
clk_prev = clk_current; // 2 real variables, storing the vakues of the clock signal in time tn and // tn+1. Imagine what will happen if the gap between tn and tn+1 are not small enuf!!!
clk_current = V(clk);
if(clk_current > th && clk_prev < th)
you have a positive edge of clock

if(clk_current < th && clk_prev > th)
you have a negative edge of clock
end

This works if your clock is an input and the simulator is not missing the clock edges. This might sound a bit confusing ::) Actually it means the gap between tn and tn+1 (mentioned above) are small enough.

2. Relax the tolerances in your cross statements.
3. Use bound_step or use max_step in your transient analysis.

Hope it helps!
Rajdeep

Title: Re: cross statement
Post by nishant22 on Jan 21^st, 2009, 7:38am

Thanks Rajdeep!
It definitely would help, for my basic concern is keeping my simulation speed intact and as events are dependent on the edges and i guess your way would work, ill try it! thnx But as a good VA practice if else or cross or delay should be avoided so i thought if there is a better way out.