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Design >> Mixed-Signal Design >> Question on 2nd Order Sigma-Delta ADC (switched cap)
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Message started by neoflash on Jan 19^th, 2009, 7:25am

Title: Question on 2nd Order Sigma-Delta ADC (switched cap)
Post by neoflash on Jan 19^th, 2009, 7:25am

Hi,

I have a question on a design of 2nd Order Sigma-Delta ADC (switched cap). The schematic is attached on the message.

The question is that the signal transfer function should not be the same as Z-2 as stated in the text book.

The problem stems from the two integrators. Both of the integrators has a
TF = Z-1 / (1-Z-1), which contains a delay. Therefore it is different from standard model of 2nd order mod whose 1st stage integrator doesn't have delay (Z-1).

I'm confused with this since this design is taken from EE247 lecture notes of Berkley. Wish people could help me understand it.

Title: Re: Question on 2nd Order Sigma-Delta ADC (switched cap)
Post by Berti on Jan 20^th, 2009, 12:10am

Hi,

I think that a "standard" 2nd order delta-sigma modulator has a NTF = (1-z^-1)². You get this transfer function by using two (delaying) integrators with transfer functions equal z^-1/(1-z^-1).

I don't really understand what's confusing you and I don't understand the transfer functions you gave (delay = z-1 ??)

Quote:

TF = Z-1 / (1-Z-1), which contains a delay. Therefore it is different from standard model of 2nd order mod whose 1st stage integrator doesn't have delay (Z-1).

Probably I have to check the Berkley lecture notes first.

Regards

Title: Re: Question on 2nd Order Sigma-Delta ADC (switched cap)
Post by neoflash on Jan 20^th, 2009, 6:55pm

The things I was ever confused is about the STF of proposed design.

If the 1st integrator has a delay in forward path (TF=Z^-1/(1-Z^-1)), therefore the STF will have a denimonator as

1-Z^-1+Z^-2.

When the 1st integrator doesn't have the delay (TF=1/(1-Z^-1)), the STF doesn't have this denominator.

I think about it twice and discussed with someone. The result is that his denominator is approximately 1 in the bandwidth of signal. Thus it just introduced negligible distortion and is ok to keep it in.

In digital implementation of the modulator, it is possible to design a delay-free integrator, therefore, this distortion can be avoided in the digital modulators.

Title: Re: Question on 2nd Order Sigma-Delta ADC (switched cap)
Post by ywguo on Jan 24^th, 2009, 1:32am

Hi neoflash,

That circuit was proposed by Prof. Bernhard E. Boser in The Design of Sigma-Delta Modulation Analog-to-Digital Converters. The gain coefficients for both integrator are not 1. Assume a1 is the gain coefficient for the 1st integrator, a2 for the 2nd integrator. One possible solution is a1 = 0.5 and a2 = 2. Then the denominator of STF is 1 rather than 1-z^-1+z^-2.

By the way, you should put the switch sequence in the post so that we can analyze the delay.

Yawei