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Measurements >> Phase Noise and Jitter Measurements >> simulate divider jitter with pnoise jitter
https://designers-guide.org/forum/YaBB.pl?num=1233801262

Message started by southofthebay on Feb 4^th, 2009, 6:34pm

Title: simulate divider jitter with pnoise jitter
Post by southofthebay on Feb 4^th, 2009, 6:34pm

Hello all,

I have some basic questions regarding jitter simulation of a simple divider. This problem has probably been beaten to death on here but I just wanted to clarify if my set up is correct.

I have a digital divide-by-2 with the following settings.

input : 200 MHz square wave
output : 100 MHz

pss setup:

beat frequency : 100 MHz
number of harmonics : 11 (will increase to get more accuracy)
accuracy defaults : moderate
additional time for stabilization : 25n

pnoise setup:

beat frequency : 100 MHz (automatically picked up from pss)
start : 1
stop : 200 MHz
maximum sideband : 11 (corresponds with number of harmonics from pss?)
output voltage : positive output node : /clkout
negative output node : none (defaults to gnd right?)
input source : none
noise type : jitter
signal : /clkout (picked up from output voltage definition)
threshold value : 0.5V (half of VDD)
crossing direction : fall (detection circuit following uses falling edge)

After the simulation finishes, I go to Results -> Main Form -> pnoise jitter

I choose:

Funciton : Jee
Signal level : rms
Modifier : Second
Integration Limits, Start Frequency (Hz) : 1, Stop Frequency (Hz) : 200M (??)

and hit Plot.

If my output frequency is 100 MHz, should I integrate from 1 to 50 MHz to get Jee? Do I need to multiply by 2?

Is this Jee value the same as that from the time domain (strobed) analysis gathered from "Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers (Aug 2006 version)? I have listed the equations below.

(Equ. 56) var(nv(tc)) = ∫[fo][/2][0]Snv(f,tc)df
(Equ. 55) Jee = √(var(nv(tc))/dv(tc)/dt)

Thanks,
south

Title: Re: simulate divider jitter with pnoise jitter
Post by Frank Wiedmann on Feb 5^th, 2009, 12:50am

You should be able to find most answers in the thread starting at http://www.designers-guide.org/Forum/YaBB.pl?num=1224609785 and the references given there. Hint: this forum also has a search function.

Some short answers: The upper integration limit should always be half the pss frequency (50 MHz in your case). Contributions from higher frequencies are included automatically through folding. The number of sidebands in the pnoise setup determines the maximum frequency from which noise contributions are folded down and included in the result. Increase it until a further increase no longer makes a significant difference (see also section 2.2 of http://www.designers-guide.org/Analysis/sc-filters.pdf). The number of sidebands in the pss setup has no effect on the jitter result.

Jee is the standard deviation of the transition time with respect to the ideal transition time. Jc for a large number of cycles is √2 × Jee because Jc includes two independent transitions at the beginning and the end of the interval.

Title: Re: simulate divider jitter with pnoise jitter
Post by southofthebay on Feb 5^th, 2009, 8:46am

Frank,

Thank you for your reply. I will also have a look at the thread you mentioned.

Regards,
south