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Design >> Analog Design >> Matching derating factor bad layout
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Message started by Visjnoe on Feb 24^th, 2009, 11:08am

Title: Matching derating factor bad layout
Post by Visjnoe on Feb 24^th, 2009, 11:08am

Dear all,

For the layout of an analog circuit there are some well-known best practices.
But what happens when you don't follow these guidelines? Can you assess this
qualitatively and if so, how?

As an example, consider a current mirror where the device sizing is OK with regard
to random mismatch/systematic mismatch.

How much would the matching be derated if one would not place these transistors close together? Or make their orientation perpendicular? Etc.
Any way to put a number on that (derating factor)?

Kind Regards

Peter

Title: Re: Matching derating factor bad layout
Post by vivkr on Feb 25^th, 2009, 12:16am

Hi Peter,

I don't believe that you can put a generic derating factor in such a case. This will likely be extremely sensitive to the processing conditions. You will probably not see a consistent derating factor even if you make a testchip.

In any case, it is often possible to follow best-practices with a minimal effort even without using common centroid and dummies.

Regards,

Vivek

Title: Re: Matching derating factor bad layout
Post by Berti on Feb 25^th, 2009, 2:16am

Peter,

I think you should distinguish between local and distance mismatch. Unfortunatly, distance mismatch is typically not characterized in the DRM and there is also only very little literature available. However, you can try to find a publication which gives number for distance mismatch for a similar technology and compare it to the local mismatch data you have from your fab.

But when you have small (especially minimum length) devices, I think that the benefit of common centroid is only limited. Dummies on the other hand I think are important due to well-proximity effects, STI etc.

Cheers

Title: Re: Matching derating factor bad layout
Post by Visjnoe on Feb 26^th, 2009, 3:21am

Thanks for your answers.
There are indeed not much papers on the subject.
Probably, if you take care of the sizing and DC biasing, you cannot deteriorate the matching that much by bad layout practice... unless you are aiming for 10b-12b performance.

Regards

Peter

Title: Re: Matching derating factor bad layout
Post by Berti on Feb 26^th, 2009, 4:31am

Probably you CAN derate the matching by bad layout - but I expect that techniques like interdigitized-structures and common-centroid won't bring much improvement unless you have very large devices.

Cheers

Title: Re: Matching derating factor bad layout
Post by superken on Feb 26^th, 2009, 10:01am

I think if you look at foundry matching data such as those from TSMC, they characterize matching of the devices based on large distance, different orientations and without dummies. That's the raw matching you're going to get, and any matching improvement efforts through good layout practice could only help. By how much? is still debatable and as long as you follow the correct biasing and sizing, the mismatch deviation won't be that substantial unless you are shooting for 8b or higher matching.