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Design >> Analog Design >> Substrate guard ring
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Message started by gary197 on Mar 2^nd, 2009, 9:06am

Title: Substrate guard ring
Post by gary197 on Mar 2^nd, 2009, 9:06am

Can anyone suggest how to build a good guard ring or multiple rings to attenuate all substrate coupling from digital CMOS into a differential PLL in 90nm CMOS technology?

Title: Re: Substrate guard ring
Post by ci on Mar 2^nd, 2009, 2:55pm

You can implement p+ shunting, pn junction, and isolating guard rings, or isolating shields made of n-type buried layer surrounded by deep trench (isolated p-wells), but I don't think any of these will completely eliminate the substrate noise.

You may consider implementing additional circuit level compensation in your PLL. It was a paper presented at DesignCon this year about active cancellation of substrate noise coupling with a VCO example, which you can find and download for free at http://www.noisecoupling.com

Regards,
ci

Title: Re: Substrate guard ring
Post by Sarig on Mar 9^th, 2009, 3:19pm

Hi,
Best is to use Deep Nwell process and place all Digital and analog in different Deep Nwell
other thing is to use Nwell ring connected to analog Vdd and inner ring connected to Analog GND in this way it will improve isolation from digital noise but remeber that this is only good for Non Epi process (so chekc what is users).

also be careful to keep min 15um from any digital contacts to the analog ring.
And last: try to build some 1st order bonding and Substrate model and simulate ac Transfer function.

Good luck,
Erez