Post by seahs on Mar 9th, 2009, 10:29am
I used the vpulse in analog. the clock is used to drive many TGs in a sample and hold amplifier. How come it became not ideal in simulation?
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https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> ideal clock not ideal in simulation https://designers-guide.org/forum/YaBB.pl?num=1236619754 Message started by seahs on Mar 9th, 2009, 10:29am |
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Title: ideal clock not ideal in simulation Post by seahs on Mar 9th, 2009, 10:29am I used the vpulse in analog. the clock is used to drive many TGs in a sample and hold amplifier. How come it became not ideal in simulation? |
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Title: Re: ideal clock not ideal in simulation Post by Andrew Beckett on Mar 9th, 2009, 2:57pm Can you post the netlist. I doubt very much what your plotting is directly the output of the vsource. Regards, Andrew. |
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Title: Re: ideal clock not ideal in simulation Post by Ken Kundert on Mar 9th, 2009, 10:00pm TGs? |
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Title: Re: ideal clock not ideal in simulation Post by seahs on Mar 9th, 2009, 10:10pm Ken Kundert wrote on Mar 9th, 2009, 10:00pm:
Transmission gates |
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