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Design >> Analog Design >> Problem designing a CS amp
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Message started by kidman on Mar 14^th, 2009, 4:00pm

Title: Problem designing a CS amp
Post by kidman on Mar 14^th, 2009, 4:00pm

I am trying to design a CS amp and I'm using the gm/id methodology in my design. I am trying to achieve a gain of 50 with no BW specs or anything.The CS amp PMOS with a current sink load (NMOS). So the gain is gm(ro//ro). If the ro1=ro2 then the gain is gmro/2.

so what I do is try to get a gmro of 100 from the PMOS and then see the ro and try to achieve it in the NMOS too. But one of 2 things happens

1- Everything goes ok but when I connect both transistors to each other to form the amplifier the gain is changed

2-the NMOS either meets the specified current without meeting the r0 or vice versa.

Any idea what could be the reason for that?

Title: Re: Problem designing a CS amp
Post by jiesteve on Mar 15^th, 2009, 1:15am

You're going to get discrepancies because in the gm/id method the plots are done assuming the transistor is in a diode-connected configuration (Vgs=Vds). But in your CS amp this is not the case with either transistor. Also, the gain will be sensitive to the input voltage and output voltage (it's not a static number). You can't really set the gain precisely in an open loop configuration -- you need to have some sort of feedback.

Usually when you're designing an amp you design it so that it has a "high enough" gain (i.e. a minimum gain). If you want precise gain then you need negative feedback.