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https://designers-guide.org/forum/YaBB.pl Other CAD Tools >> Physical Verification, Extraction and Analysis >> NMOS LVS https://designers-guide.org/forum/YaBB.pl?num=1237201909 Message started by Ian on Mar 16th, 2009, 4:11am |
Title: NMOS LVS Post by Ian on Mar 16th, 2009, 4:11am Hi, All, I'm currently working on a transistor layout. When I did the LVS for an individual transistor (the substrate is tied to the source terminal), it reported three errors on missing ports (gate, source and drain). I actually defined these ports by "connectivity->update->components and nets->layout generation->generate I/O pins", and the pin labels are also defined in the 'pin' layer. When I put this transistor in a higher-level circuit block, it reported the transistor part is correct, although with a warning about "Extra ports in source: Gate". Now I'm confused. Anybody encountered similar problem? Best Regards, Ian |
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