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Simulators >> Circuit Simulators >> Offset-Simulation of Comparators paper / implementation in eldo
https://designers-guide.org/forum/YaBB.pl?num=1237223739

Message started by jiesteve on Mar 16^th, 2009, 10:15am

Title: Offset-Simulation of Comparators paper / implementation in eldo
Post by jiesteve on Mar 16^th, 2009, 10:15am

I have read the white paper on Offset-Simulation of Comparators on this site and I would like to implement it using eldo and a post-processing script. I'm wondering if anyone has already done this here and is willing to share their eldo input deck and/or post-processing script?

Thanks in advance.

Title: Re: Offset-Simulation of Comparators paper / implementation in eldo
Post by weber8722 on Mar 17^th, 2009, 7:30am

Is this for a latched comparator (i.e. with clock) or for a continous-time comparator. The TB are quite different.

In Cadence ahdlLib there is a veriloga view helping to implement such TB.

Bye Stephan

Title: Re: Offset-Simulation of Comparators paper / implementation in eldo
Post by jiesteve on Mar 17^th, 2009, 10:33am

This is for a latched comparator.

Title: Re: Offset-Simulation of Comparators paper / implementation in eldo
Post by jiesteve on Mar 17^th, 2009, 2:34pm

Nevermind, I was able to code up a simple perl script and eldo testbench.

Thanks anyway.