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Design >> Mixed-Signal Design >> On chip BIST architectures for Mixed Signal Design.
https://designers-guide.org/forum/YaBB.pl?num=1237796925

Message started by Mahavir on Mar 23^rd, 2009, 1:28am

Title: On chip BIST architectures for Mixed Signal Design.
Post by Mahavir on Mar 23^rd, 2009, 1:28am

Why aren't the on-chip testing methods so popular with mixed signal design as they are with digital design?

Title: Re: On chip BIST architectures for Mixed Signal Design.
Post by Berti on Mar 24^th, 2009, 12:59am

I think because they are more difficult to implement.

Cheers

Title: Re: On chip BIST architectures for Mixed Signal Design.
Post by rf-design on Mar 24^th, 2009, 10:20am

Analog BIST are getting more popular if complexity allows a clean D/A/D signal path. Typical is today to access internal bias voltages and make loop connections involving DACs and ADCs. Selective switch on of bias and some similar techniques are used for test support.

Title: Re: On chip BIST architectures for Mixed Signal Design.
Post by loose-electron on Apr 5^th, 2009, 5:28pm

In an ideal world, having all chips do BIST would b great. The reality is generally limited due to time to market limitations. I can get a digital scan chain into a digital system quickly, doing BIST for analog things often requires a time/design/area/power investment.

Title: Re: On chip BIST architectures for Mixed Signal Design.
Post by Peruzzi on Apr 6^th, 2009, 7:19am

Mahavir:

To get value out of your time/design/area/power investment in mixed signal BIST (also known as calibration, offset correction, self-tuning, alignment):
* Plan your mixed signal BIST earlier rather than later
* Make the BIST observable and controlable (even if indirectly) from outside the package. At least for first Silicon on your first chip using M/S BIST because you'll have to convince yourself and your customers that it's actually working (or for debug)
* Accept the fact that you won't be able to simulate the entire circuit at the device level, so plan to use AMS simulation and behavioral models
* Begin with high level Verilog-AMS or VHDL-AMS models, then refine the models as you develop the design
* Validate your models versus your schematics
* When practical, evolve your models to use a signal flow approach and real rather than electrical quantities. This will greatly speed up your simulations. But beware -- it must be done right -- so validate, validate, validate
* Consider bringing in a battle-scarred consultant (like me ;-) to help you through the process rather than assigning this absolutely necessary and critical, but tedious, task to an overburdened circuit designer

More and more IC and SOC designs are using M/S BIST. Its presence is now a competitive advantage, and soon will be a requirement.

Best of luck!

Bob P.
Peruzzi@RPeruzzi.com