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Design >> RF Design >> pattern gound shielding
https://designers-guide.org/forum/YaBB.pl?num=1237895815

Message started by analog_cha on Mar 24^th, 2009, 4:56am

Title: pattern gound shielding
Post by analog_cha on Mar 24^th, 2009, 4:56am

I am a novice to this topic.
How do we do pattern ground shielding for an inductor??
I referred some paper which says that the patterns should be done tsuch that they are orthogonal to the spiral, so that it reduces the image currents and hence the ohmic losses.
But in case of an octogan, how can it be done??

If you have any good documents on this, pls share.
Thanks.

Title: Re: pattern gound shielding
Post by loose-electron on Apr 5^th, 2009, 4:48pm

The isolation shielding of reactive passive elements sparks a lot of debate and opinion. Suggest that you look at putting it together in an EM modeling tool and experiment with the possibilities there. At least then the results are quantitative and not based upon opinions.

Title: Re: pattern gound shielding
Post by chenyan on Apr 16^th, 2009, 6:36am

Hi Loose-electron,

Do you know if people are still using pattern ground shielding for on-chip inductors? I think it is used quite rarely.

Could you please suggest some reference about the debates? Thanks a lot!

cheers
chenyan

Title: Re: pattern gound shielding
Post by pancho_hideboo on Apr 16^th, 2009, 6:41am

rfmems wrote on Apr 16^th, 2009, 6:36am:

Do you know if people are still using ? I think it is used quite rarely.

If we see chip photos in ISSCC-2009, almost all use pattern ground shielding for on-chip inductors.

I also use pattern ground shielding for on-chip inductors using Cadence VPCD(Virtuoso Passive Component Designer).

Title: Re: pattern gound shielding
Post by chenyan on Apr 16^th, 2009, 6:58am

pancho_hideboo wrote on Apr 16^th, 2009, 6:41am:

Hi pancho_hideboo, which ISSCC paper do you mean. I had a quick glance at the ISSCC2009 DVD pll session, did not find any patterned ground shield.

Anyway since you are still using them in design. Could you please share some experience, how much the quality factor can be improved (at which frequency)? Also if you can, some information of the technology you are using.

Thanks a lot
chenyan

Title: Re: pattern gound shielding
Post by pancho_hideboo on Apr 16^th, 2009, 7:13am

rfmems wrote on Apr 16^th, 2009, 6:58am:

Hi pancho_hideboo, which ISSCC paper do you mean. I had a quick glance at the ISSCC2009 DVD pll session, did not find any patterned ground shield.

Wireless and RF building blocks.

rfmems wrote on Apr 16^th, 2009, 6:58am:

Anyway since you are still using them in design. Could you please share some experience, how much the quality factor can be improved (at which frequency)? Also if you can, some information of the technology you are using.

150nm and 130nm CMOS Process which have five metals and one thick metal.
These are not major foundry processes.

Quality factor is little improved as simulation.
Actual measurements also show little improvement in phase noise but it is not drastical improvement.

Title: Re: pattern gound shielding
Post by chenyan on Apr 16^th, 2009, 8:12am

Hi pancho_hideboo,

Thanks. I think for blocks like lna, it is important to isolate the interferes from substrate, that is why PGS is more ofen used.

For VCO design, as the Q is not obviously improved, it is really used in rare cases. Of course isolate the interferers from substrate is also important for VCO. However, this can be handled with much easier solutions.

Title: Re: pattern gound shielding
Post by pancho_hideboo on Apr 16^th, 2009, 8:23am

rfmems wrote on Apr 16^th, 2009, 8:12am:

I think for blocks like lna, it is important to isolate the interferes from substrate, that is why PGS is more ofen used.

For VCO design, as the Q is not obviously improved, it is really used in rare cases. Of course isolate the interferers from substrate is also important for VCO. However, this can be handled with much easier solutions.

My opinios are:
- PGS don't result in any bad effects at least.
- So it is not valueless to use PGS even for VCO design.
- Many major foundary PDK provide PGS for inductor.

Title: Re: pattern gound shielding
Post by Terence on Apr 17^th, 2009, 3:53am

There are two side-effects of PGS:

1.) One dedicate clean AC ground pad is required for each inductor
2.) Self-resonance freq is degraded.

Actually, we do not use PGS very often.

Title: Re: pattern ground shielding
Post by pancho_hideboo on Apr 17^th, 2009, 4:02am

Terence wrote on Apr 17^th, 2009, 3:53am:

1.) One dedicate clean AC ground pad is required for each inductor

What do you mean ?

Terence wrote on Apr 17^th, 2009, 3:53am:

2.) Self-resonance freq is degraded.

I agree to this effect.

Title: Re: pattern gound shielding
Post by RFICDUDE on Apr 17^th, 2009, 11:37am

I believe they mean that if you really need the PGS to improve inductor to substrate isolation, then you need a dedicated, "clean," low impedance ground connection just for the shield. Otherwise the shield is not providing a good AC ground path for the substrate noise.

If the ground shield is tied to the local circuit ground, then it is probably not much more effective than using wide guard rings around the whole circuit to try and shunt off substrate noise.

Title: Re: pattern ground shielding
Post by pancho_hideboo on Apr 18^th, 2009, 12:39am

RFICDUDE wrote on Apr 17^th, 2009, 11:37am:

I agree to your opinions if I use PGS as isolation of substrate noise.

But if I want to get high Quality factor of inductor, I think that Ground of PGS should be opened, that is, Patterned Floating Shield should be used.

How do you think ?

Title: Re: pattern gound shielding
Post by rfmems on Apr 24^th, 2009, 6:35am

Hi pancho_hideboo,

Your floating PGS is a good point . In this case I guess the parasitic cap from inductor to floating shield in series with the cap between shield to substrate, am I right? With this method, I suppose you can reduce the Cp from ind to ground, but to which extent?

Also, I think whether to using PGS depends on the working frequency as well. Since small eddy current still exists and will reduce the inductance and Q at high frequency. Acoording to my simulation, 1-2GHz is fine, but higher you see the internal inductance start to fall below the same geomtry without PGS.

So maybe your inductor works in the range of 1-2GHz or its proximity. Let me know if I was wrong.

Title: Re: pattern ground shielding
Post by pancho_hideboo on Apr 24^th, 2009, 8:39pm

chenyan, thanks for comments.

rfmems wrote on Apr 24^th, 2009, 6:35am:

Your floating PGS is a good point.
In this case I guess the parasitic cap from inductor to floating shield in series with the cap between shield to substrate, am I right?

Right.

rfmems wrote on Apr 24^th, 2009, 6:35am:

With this method, I suppose you can reduce the Cp from ind to ground, but to which extent?

If top two metals are enough far from substrate, there is almost no reduction of Cp even if I use floating PGS.
But they are not so far from substrate in my cheap process.

rfmems wrote on Apr 24^th, 2009, 6:35am:

Acoording to my simulation, 1-2GHz is fine,
but higher you see the internal inductance start to fall below the same geomtry without PGS.

What do you mean by "the internal inductance" ?
http://www.designers-guide.org/Forum/YaBB.pl?num=1205240723/1#1

rfmems wrote on Apr 24^th, 2009, 6:35am:

So maybe your inductor works in the range of 1-2GHz or its proximity. Let me know if I was wrong.

Operation frequency of my application is 2.4GHz.

Title: Re: pattern gound shielding
Post by rfmems on Apr 25^th, 2009, 3:46am

Hi pancho_hideboo,

By internal indutance I mean the inductance excluded the factor of 1/(1-w^2LC), the self resonance factor.

I guess it is the same concept in that thread you added.

Title: Re: pattern gound shielding
Post by RFICDUDE on Apr 27^th, 2009, 8:02pm

I am a little confused by usefulness of a floating patterned ground shield.

What is the performance benefit of placing a floating patterned conductive shield under the inductor?

I would think that this provides no benefit because the RF currents in the shield have no place to go. This should look like a partially nonconductive dielectric (due to the pattern) layer.

Thanks

Title: Re: pattern ground shielding
Post by pancho_hideboo on Apr 28^th, 2009, 1:45am

RFICDUDE wrote on Apr 27^th, 2009, 8:02pm:

What is the performance benefit of placing a floating patterned conductive shield under the inductor?

If we will reduce loss due to current flowing in substrate, metal patterns under inductor which have slits disturbing current low are useful.
But this metal patterns increase parasitic capacitor of inductor if they are connected to ground.
If this metal patterns are not connected to ground, parasitic capacitor doesn't increase compared to grounded metal patterns.

On the other hand, from point of view of substrate noise coupling shield, we have to use grounded metal patterns not floating metal patterns.

Title: Re: pattern gound shielding
Post by RFICDUDE on Apr 28^th, 2009, 7:25am

Hmm, do you have a reference or a data point that supports the assertion that the floating shield reduces losses by preventing eddy current losses in the substrate?

The shield would have to somehow terminate the inductive field lines with less loss than currents induced in the substrate.

I am just curious how much benefit there is versus the modeling and layout effort to shield the inductor.

Thanks

Title: Re: pattern gound shielding
Post by Peruzzi on Apr 28^th, 2009, 10:07am

All,

Please forgive my butting in on this topic so late on page two, but I sense some confusion with terminology. Maybe I'm the only one confused.

In deep sub-micron technologies there is a physical requirement for somewhat evenly spaced metal level coverage on the metal layers -- literally so the stacked layers won't be too bumpy. So digital layout designers came up with the idea of the floating metal islands which don't bother digital electrical performance. As far as I know, digital designers ignore the parasitics due to the metal fill.

RF and Analog designers can't ignore these parasitics. More by instinct than anything I can prove, I'm not for allowing them to float and prefer to see these metal islands grounded. Making use of their L or C properties seems creative too. My point is, we're stuck with them, like it or not, and can only choose between trying to make them innocuous or putting them to use.

Or are you discussing something else altogether, where the floating or grounded patterned ground shield is optional?

Thanks,

Bob P.
www.RPeruzzi.com

Title: Re: pattern gound shielding
Post by rfmems on Apr 28^th, 2009, 11:38am

Hi Peruzzi,

Actually for on-chip inductors, it is not necessary to have ground shield underneath. What you were saying is metal filling for designing rules of metal density. But violation is not strictly forbidden, one exception case is on-chip inductor.

Title: Re: pattern gound shielding
Post by Peruzzi on Apr 28^th, 2009, 11:42am

Hi RFMems,

Thank you for explaining the difference in a tolerant manner. My curiosity often outweighs my fear of embarrassment :)

Best regards,

Bob P.

Title: Re: pattern gound shielding
Post by rfmems on Apr 28^th, 2009, 2:29pm

RFICDUDE wrote on Apr 28^th, 2009, 7:25am:

Hi RFICDUDE,

The PGS cuts the plate into strips so the eddy current can hardly flow. Floating PGS would reduce the electrically coupled capacitance to substrate (how effective depends on technologies). On the other hand, rf current can penetrate into substrate with PGS floating. So you see some trade-offs here. And whether it is useful depends on lots of factors.

For RF circuits, every dB counts. So if the PGS is helpful, surely it worths the work of modelling. PGS as I saw from this year's ISSCC, is still used for applications around 1-2GHz. But for higer frequencies (>=4G), it is almost never used. And it works better for LNA than VCO since PGS harms the tunability.

pancho_hidebo, since you have practical experiences on floating PGS, I hope you can add your comments to RFICGUIDE's questions, and correct me if I was wrong.