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Simulators >> AMS Simulators >> simulating using Mentor-tools
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Message started by Prateek on Mar 25^th, 2009, 10:34pm

Title: simulating using Mentor-tools
Post by Prateek on Mar 25^th, 2009, 10:34pm

in designer-guide.org the examples given for vams are for simulating it from cadence AMS designer. CAn any one plz plz tell how to do the same using Mentor-Tools ADMS
its very imp.
i'm attaching a example for reference

Title: Re: simulating using Mentor-tools
Post by Paul Floyd on Apr 22^nd, 2009, 1:57am

Hi

Which version of Questa ADMS are you using?

To convert netlists, there is the tool spect2el (e.g.,
spect2el -in_dir . -file_list run.scs). Perhaps that's a bit overkill for such a simple netlist.

Here are the files that I used:

commands.sh [equivalent of run-me, remove the -c option to vasim to have the equivalent of run-me-with-gui]
#!/bin/sh

rm -rf my_connectlib
valib my_connectlib
vasetlib my_connectlib

# compiling the connect rules
valog -work my_connectlib connectrules.vams

rm -rf worklib
valib worklib
vasetlib worklib

valog adc.vams
valog testbench.vams

vasim -c -cmd run.cmd -do run.do

run.do [equivalent of run.tcl]
add wave -r *
run 100us
exit

run.cmd [equivalent of run.scs]
*
.model testbench macro lang=verilogams

Y1 testbench
+ port : T1

v1 T1 0 sin (0.5 0.5 1meg 0 0)
.tran 100us 100us

And finally
testbench.vams [modified to put sinewave vsource in netlist]
`timescale 10ns / 10ps
`include "disciplines.vams"

module testbench (in);
electrical in, gnd;
input in;
ground gnd;
reg clk;
wire [0:7] out;
integer ii;
reg [0:7] plot_out;

initial clk=0;

always #1 clk=~clk;

always @(out) for (ii=0; ii<8; ii=ii+1) plot_out[ii] <= out[7-ii];

adc adc0 (out, in, clk);
//vsource #(.type("sine"), .ampl(0.5), .dc(0.5), .freq(1M)) v0 (in, gnd);
endmodule

Paul

Title: Re: simulating using Mentor-tools
Post by Prateek on Apr 22^nd, 2009, 10:48pm

thnks a ton man,,, u saved me :)
u r simply god to me ;)