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Design >> Analog Design >> load transient response improvement of LDO
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Message started by khajaahmad on Mar 27^th, 2009, 6:35am

Title: load transient response improvement of LDO
Post by khajaahmad on Mar 27^th, 2009, 6:35am

hi, i need to find a relationship between open loop phase margin of LDO
and closed loop load transient response of LDO, but for the problem i am facing is for my LDO input is constant but load is changing , so which open loop transfer function I should take is it Vo(s)/Vi(s), by simply breaking the loop and applying Vi at input positive input of error amplifier or it is other thing????
thanks in advance .
My LDO is attached here.

Title: Re: load transient response improvement of LDO
Post by thechopper on Mar 27^th, 2009, 7:54pm

The open loop gain over frequency for your LDO will also set the output impedance of your LDO over frequency.
Such output impedance will be the one setting the response to the load variations on your regulated line.
So you should run and ac analysis and analyzing VO(s) / Io(s) where Io (s) is the current entering the output node of the LDO.
After than you can characterize the LDO response to load variations by considering the output impedance it is presenting to the external load.

Regars
Tosei

Title: Re: load transient response improvement of LDO
Post by raja.cedt on Apr 6^th, 2009, 12:38pm

hi,
i didn't get your question properly,if you make output pole dominant and keep first non dominant pole at 2* times of the UGB,then you can directly find the relation.if you have any question,please let me know.

Thanks,
rajasekhar.

Title: Re: load transient response improvement of LDO
Post by bharat on Apr 13^th, 2009, 8:53pm

Tosei,
The Io(s) is keep on varying from 2 mA to 10 mA. Therefore when you say VO(s) / Io(s), Io(s) is vriable.
Also, even if going for worst case Io(s); for pole location 10mA is worst case, for gain margin 2mA is worst case.

Rajasekhar,
you make output pole dominant
The dominant pole is not fixed if we make output as dominant, because due to change in current the pole location will move and hence UGBW and hence Phase Margin.

Title: Re: load transient response improvement of LDO
Post by thechopper on Apr 14^th, 2009, 7:07pm

bharat wrote on Apr 13^th, 2009, 8:53pm:

Hi bharat,

What you are suggesting as different levels of Io (2-10ma) are different quiescent points and correspond to large signal conditions. When referring to Io(s) I was referring to small signal conditions, which is the one that corresponds to consider when analyzing poles location, stability, etc.
Ideally such stability conditions should be analyzed for ANY possible quiescent point.

Hope this helps
Tosei

Title: Re: load transient response improvement of LDO
Post by raja.cedt on Apr 15^th, 2009, 6:43am

hi Tosei,
even i got same thought.so by finding stability using poles/zeros we are assuming that all bias voltages/currents are fixed....my question is do we have to run for all bias voltages are any other way to get rid of many simulations?But if i know that i am using my circuit for a particular range of bias then its fine,i can run for those simulations only.Lets say in this regulator at what current we have to simulate?I think at higher current less loop gain and low frequency pole will come,so this is the best case, so if i simulate at low current thats fine?
correct me if am wrong

Thanks,
Rajasekhar.

Title: Re: load transient response improvement of LDO
Post by thechopper on Apr 15^th, 2009, 5:57pm

raja.cedt wrote on Apr 15^th, 2009, 6:43am:

hi

my question is do we have to run for all bias voltages are any other way to get rid of many simulations?But if i know that i am using my circuit for a particular range of bias then its fine,i can run for those simulations only.Lets say in this regulator at what current we have to simulate?I think at higher current less loop gain and low frequency pole will come,so this is the best case, so if i simulate at low current thats fine?
correct me if am wrong

Hi Rajasekhar,

In theory you should run the ac or stability analysis for ALL the possible operation quiescent points. However the vast majority of the circuits that work under a certain range of quiescent points behave in such a way that usually it suffices with analyzing stability at the extremes of such range. This approach assumes the stability variations accross the different operation quiescent points is gradual on monothonic. If these requirements were not met then you might be missing a stability condition at a particular quiescent point that could be critical.
I think for the case of the LDO you should be fine by checking the stability at the extremes of the Io range.

Regards
Tosei