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Design Languages >> Verilog-AMS >> Is it possible to make verilog-A/AMS modules analysis-sensitive?
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Message started by Aigneryu on Mar 29^th, 2009, 6:22am

Title: Is it possible to make verilog-A/AMS modules analysis-sensitive?
Post by Aigneryu on Mar 29^th, 2009, 6:22am

Hi,

I have some frequency meters in my testbench for transient simulation; however, these frequency meters have hidden states, and I want to skip the part with hidden states in them during the PSS simulation. Is it possible?

Sincerely,

Title: Re: Is it possible to make verilog-A/AMS modules analysis-sensitive?
Post by Geoffrey_Coram on Mar 30^th, 2009, 8:51am

How about this?

Code:

if (analysis("pss", "pac", "pnoise")) begin
// set freq meter variables to 0 to avoid hidden state
end else begin
// frequency meter code
end