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Design >> Analog Design >> Subthreshold design help
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Message started by oermens on Apr 2^nd, 2009, 11:47am

Title: Subthreshold design help
Post by oermens on Apr 2^nd, 2009, 11:47am

Hi, I am interested in sub-vth analog/rf design and I am wondering how to relate my hand calculations using EKV model to simulation results using BSIM4 models. Mainly I am interested in how much stock I should put into the 'region' parameter. I want to design for weak inversion, which Vittoz says is the same as the more common term, subthreshold. When I do a DC sweep of Vgs I find the region for which the device is in subthreshold (region 3), but when I apply a ramp input (Vpulse with long rise time) and plot the region parameter from transient result, the value of Vg for which the device is in region 3 is not the same as the result obtained in DC. Is this correct? Should I not consider this parameter and only focus on Inversion Coefficient? Also the spectre model guide states that in subthreshold the only device capacitance is Cgb, however I am seeing nonzero capacitances for all capacitances whose values are greater than Cgb by several orders of magnitude in some cases (self-capacitances on the order of pF). What is the reason for this?

Title: Re: Subthreshold design help
Post by loose-electron on Apr 5^th, 2009, 5:04pm

Many model sets are done at the foundry that do not have the parameters properly set for sub threshold and micro currents.

Go get the foundry data on you models and see how low you have data based on silicon, actually getting used in the models.

Title: Re: Subthreshold design help
Post by wladek on Apr 29^th, 2009, 5:17am

let me recommend following readings:

D. Stefanovic and M. Kayal 'Structured Analog CMOS Design'; Series: Analog Circuits and Signal Processing, 2009, ISBN: 978-1-4020-8572-7
Paul G.A. Jespers; 'The gm/ID Design Methodology for CMOS Analog Low Power Integrated Circuits'; ISBN: 978-0-387-47100-6
D. M. Binkley; 'Tradeoffs and Optimization in Analog CMOS Design', ISBN: 978-0-470-03136-0