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Design >> Analog Design >> Load current of bandgap voltage reference
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Message started by misc on Apr 8^th, 2009, 3:45am

Title: Load current of bandgap voltage reference
Post by misc on Apr 8^th, 2009, 3:45am

Dear all,
i am designing a current summing voltage refreence for and ADC . My requirement is 1.4Volt output with 50uA load curent. But when i tried simulation for load regulation using the 50ua load current my Vref is oscillationg very badly. Please some suggest me how to improve the load current variation for my requirement.

Thankx in dvance
raags

Title: Re: Load current of bandgap voltage reference
Post by Berti on Apr 8^th, 2009, 4:24am

If you really expect a useful answer you should post a schematic.

Cheers

Title: Re: Load current of bandgap voltage reference
Post by misc on Apr 8^th, 2009, 5:56am

Hi,

i have atatched the schematic for your reference.

thanks in advance
raags

Title: Re: Load current of bandgap voltage reference
Post by Berti on Apr 8^th, 2009, 7:52am

What kind of ADC do you use?

A bandgap is generally not well suited to drive loads. It is therefore not surprising that you have problems. You should add an additional buffer.

Cheers

Title: Re: Load current of bandgap voltage reference
Post by PaloAlto on Apr 8^th, 2009, 8:40am

Sorry, I didn't understand it at first :D Now, I see your point, you are trying to draw 50uA from the bandgap voltage node. No, you shouldn't do that. Think about it, as Berti says, if you try to get 50uA from that node you are subtracting it from the current that should flow into the resistor to generate the voltage level. So you are changing it. What tou should do is add some kind of buffer. Even a very small one, since 50uA is almost nothing

Title: Re: Load current of bandgap voltage reference
Post by misc on Apr 8^th, 2009, 8:05pm

Dear berti and paloAtto,

thank you for the information. To be clear i am using this bandgap for SAR ADC reference voltage generation. . We are trying to improve the accuracy of ADC by implementing onchip BGR along with SAR ADC. We thought of using a buffer at the output of BGR, but we are worried about the power consumption. We are having a very stringent power budget including BGR and ADC of about 300u. already my BGR is consuming a power of 80u and and i am really worried about power if i use another buffer in between. So any inputs on addressig these issues would be of great help.

TIA
raags

Title: Re: Load current of bandgap voltage reference
Post by solidstate on Apr 9^th, 2009, 1:56am

80uA ( or uW?) seems like a lot for a bandgap reference.. what determines the need for that current?

Title: Re: Load current of bandgap voltage reference
Post by misc on Apr 9^th, 2009, 2:53am

Dear solidstate,

Since i am using an opamp based Bandgap reference the current drawn is 80uA as of now. Any info on imprving load regulation of Bandgap reference without an additional buffer amplifier would be appreciated.

TIA
raags

Title: Re: Load current of bandgap voltage reference
Post by Berti on Apr 9^th, 2009, 3:26am

Raags,

I think you take the wrong approach. You should try to reduce the power consumption of your bandgap and spend that for a buffer.
I don't think that using the bandgap to drive the reference of a SAR will result in a power efficient solution.

Cheers

Title: Re: Load current of bandgap voltage reference
Post by misc on Apr 9^th, 2009, 3:38am

dear berti,

i am using a resistor network to generate the different voltages required for SAR ADC which will vary with VDD variations. I want to reduce this variations using a bandgap voltage reference. If i am using a buffer with bandgap reference the output of buffer is coupled with VDD variations again and i might loose the accuracy. So am i looking for a voltage refence for my ADC to improve the accuracy. any info on this is higly appreciated.

TIA
raags

Title: Re: Load current of bandgap voltage reference
Post by Tlaloc on Apr 14^th, 2009, 12:39pm

I agree with Berti. You should be able to greatly reduce the current consumption in the bandgap and use the leftover for a buffer. I don't understand your concern about using a buffer though. You will have the PSRR modify the output of the buffer, but it is still very strongly coupled to the bandgap voltage, not the supply voltage. In short, when your Vbg is generated from a current, that leg can have no load current, or you will have large errors.

Also, why did you choose this architecture? Have you looked at the variation of the output due to offsets of the amplifier? It can vary by quite a bit. There may be other architectures that would better fit your requirements.