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Design >> Analog Design >> Samle and hold and ADC
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Message started by seahs on Apr 8^th, 2009, 9:56pm

Title: Samle and hold and ADC
Post by seahs on Apr 8^th, 2009, 9:56pm

I am designing a double sampling SHA(Sample and Hold Amplifier), the clock is 200MHz, which is equivalent to 400MHz in normal SHA. The signal is 40MHz.

The measured 4th, 6th, 9th and 11th harmonics are very high, which may be due to the intermoduation of clock and signal.

I read from a paper which says the those harmonics will not effect the performace and can be neglected.

Can anybody give some information why it is so?

Thanks a lot!

Title: Re: Samle and hold and ADC
Post by raja.cedt on Apr 8^th, 2009, 10:43pm

hi,
i think you have lot of non linearity in your S/H ckt,so better keep Vgs of sampling transistor is constant irrespective of signal variations...I guess the following paper may useful.And please post your S/H circuit.

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter A. Abo and P. Gray, IEEE Journal of Solid-State Circuits, May 1999
check fig 7 in that ..

Thanks,
rajasekhar.

Title: Re: Samle and hold and ADC
Post by vivkr on Apr 8^th, 2009, 11:36pm

seahs wrote on Apr 8^th, 2009, 9:56pm:

Please be so kind as to post some concrete information (paper reference, summary of arguments you think would make these distortion components irrelevant). Otherwise, nobody can advise you. In any case, I fail to see why large distortion in the sample-and-hold is noncritical.

Regards,

Vivek