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Design >> Analog Design >> [ECE264][Q2] Regarding the biasing network for Triple-Cascode Opamp?
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Message started by NiceFeng on Apr 12^th, 2009, 1:05am

Title: [ECE264][Q2] Regarding the biasing network for Triple-Cascode Opamp?
Post by NiceFeng on Apr 12^th, 2009, 1:05am

Dear All,

In this post, I want to consult the biasing network for Triple-Cascode Opamp as shown in the attached slide.

It seems there is some pattern in this basing network, for example, current in M_b2, M_b4 and M_b6 are the same as 2I_b. Current in M_b1, M_b3, M_b5 are 6I_b, 4I_b and 2I_b.

Apparently, since M_b2, M_b4 and M_b6 are diode connected. M_b1, M_b3, M_b5 are in linear region.

Here are two questions : 1) How this biasing network works? 2) What's special advantage of this biasing network?

Thanks in advance!

Feng

Title: Re: [ECE264][Q2] Regarding the biasing network for Triple-Cascode Opamp?
Post by LeeX on Apr 12^th, 2009, 10:02pm

Hi, NiceFeng
I think this is one of the high-swing cascode biasing schemes.
The advantage is high output swing. In other words, every transistor is biased to the minimal Vgs it needs to stay in saturation, hence the maximum output swing is obtained at the output node.

Here is how it works,
As you observed, the current through Mb1, Mb3, Mb5 is 6Ib, 4Ib and 2Ib, but the size of Mb1, Mb3, Mb5 is also 6, 4 and 2, so they have the same nominal Vgs.

For Mb2, Mb4 and Mb6, they are sized very large so their Vgs is approximately Vt.

Then, for Vm1, it is Vic-Vt, the minimal voltage needed at the drains of M1 and M2 for them to stay in saturation. And Vb1 is Vic-Vt+Vgsb3, so M3 and M4 are biased such that the voltage at their sources is Vm1. The same idea applies to Vb2.

Because Mb2, Mb4 and Mb6 have very large sizes, Mb1, Mb3, Mb5 are on the verge of saturation region.

Hope this solves your problem.

Title: Re: [ECE264][Q2] Regarding the biasing network for Triple-Cascode Opamp?
Post by NiceFeng on Apr 13^th, 2009, 1:44am

Hi, Mr.Lee,

Thanks a lot for your inputs.

Do you mean we should make sure V_ds of M_b1, M_b3 and M_b5 match with that of M_eb, M₂ and M₄?

In that case, the size of M_b1, M_b3 and M_b5 has to be carefully designed, while the size of M_b2, M_b4 and M_b6 can be propotial to that of M₂ (size of M_b2 has to be somewhat smaller ?), M₄ and M₆ according to the current ratio.

Does my concern make sense?

Thanks for helps.

Kind Regards,
Feng

Title: Re: [ECE264][Q2] Regarding the biasing network for Triple-Cascode Opamp?
Post by raja.cedt on Apr 13^th, 2009, 5:39am

hi Feng,
Sizes of Mb2,Mb4,Mb6 are based on the amplifier requirement and you have to design Mb1,Mb3,Mb5 sizes 1/3 of the Mb2,Mb4,Mb6, because they have to be in triode region at the same time their Vds is vdsat with Vgs is Vt+2*vdsat.

Regarding biasing point of view this biasing scheme to match vds of the main transistors.And one simple answer for this high swing structure is its a simple diode connected load with higher loop gain.

Thanks,
rajasekhar.

Title: Re: [ECE264][Q2] Regarding the biasing network for Triple-Cascode Opamp?
Post by LeeX on Apr 13^th, 2009, 5:47am

Sorry, I made a mistake by saying "the size of Mb1, Mb3, Mb5 is also 6, 4 and 2, so they have the same nominal Vgs", it does not make much sense.

First, the Vic is the common mode voltage for the input pair M1 and M2, which I assume you have already known.

The goal here is to bias M4 and M6 so that their source voltages are Vx+Vdsat2 (which equals to Vic-Vt) and Vx+Vdsat2+Vdsat4 (Vic -Vt + Vds4), respectively. Vx here is the voltage at the drain of Meb. Note that these two voltages are the minimal for M2, M4 and M6 to stay in saturation region.

The size of Mb1 should be chosen such that the Vgsb1 with a current of 6Ib, should be Vic. Because Mb2 is quite large, its Vgsb2 almost equals to Vt, so Vm1=Vic-Vt.

Now, Vb1 = Vm1 + Vgsb3 and we need Vb1 = Vm1 + Vgs4, all we have to do is to make sure Vgsb3 = Vgs4. So we size Mb3 with a current of 4Ib to have the same Vgs with M4 when half of the current through Meb is flowing through it. Again, Mb4 is quite large, so Vm2 = Vm1 + Vgsb3 - Vt = Vic - Vt + Vds4.

Vb3 is pretty much the same here.

Note that the same current, 2Ib is flowing through Mb2, 4 and 6. You just need to make them fairly large to ensure their Vgs is approximately Vt, which is all we need from them.

Title: Re: [ECE264][Q2] Regarding the biasing network for Triple-Cascode Opamp?
Post by raja.cedt on Apr 13^th, 2009, 6:44am

hi LeeX,
some clarification based on your reply,is really we need Mb4 big..i think it is pretty same as Mb4,again it is debatable because generally people bias at same this stage with same current as would bias the main amplifier,may be you think to reduce the power wasted in the biasing stage...
Another question is this biasing is good way to do,because we can club all these stacks in one but in that case two transistor will operate in triode region still it will give decent bias?correct me if am wrong?

Thanks,
Rajasekhar.

Title: Re: [ECE264][Q2] Regarding the biasing network for Triple-Cascode Opamp?
Post by LeeX on Apr 14^th, 2009, 6:36am

Hi, Rajasekhar

Title: Re: [ECE264][Q2] Regarding the biasing network for Triple-Cascode Opamp?
Post by LeeX on Apr 14^th, 2009, 6:46am

Hi, Rajasekhar

I did not quite catch the first one, did you mean that why Mb4 should be big? If that was the case, it has to be big to ensure a Vgs approximately equal to Vt. That is not intended to save power.

In this biasing, M2, M4 and M6 will be on the verge of saturation, which may not be very reliable in practice. But I think you can purposefully bias them to a little higher voltage than necessary. For example, you could reduce the size of Mb1, 3, 5, so that they have a slight larger Vgs than M2, 4 and 6. But I am not sure if this scheme has other issues.