The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> AMS Simulators >> Power connection for verilog modules
https://designers-guide.org/forum/YaBB.pl?num=1239667591

Message started by R. Zakai on Apr 13^th, 2009, 5:06pm

Title: Power connection for verilog modules
Post by R. Zakai on Apr 13^th, 2009, 5:06pm

I have what might be a very basic question for most of you.

I can not seem to get vdd/gnd delivered to the verilog blocks in my AMS test bench. The verilog code has no mention of supply connections so I thought it must be defined implicitly through the netlister options in the ADE window but that does not help either. Digital components in my test bench appears to be unpowered. Is there some other include file or setup step I am missing here? Here is a basic code example. It might give people here more clues as to what I am doing wrong or missing.

Thanks,
Rehan

// Created by ihdl
`timescale 1ns/1ps

`celldefine

module inv0d0 (ZN, I);
output ZN;
input I;
`protect

specify
// Pin-to-pin timing.
(I => ZN) = (`inv0d0_i_hl_zn_lh,`inv0d0_i_lh_zn_hl);
endspecify

// Gate-level description.
not _i0 (ZN,I);

`endprotect
endmodule

`endcelldefine

Title: Re: Power connection for verilog modules
Post by boe on Apr 15^th, 2009, 7:01am

R. Zakai,
Verilog is quite old and purely digital, so signal levels are modeled as LOW, HIGH, X and Z (different drive strengths are possible for all, though), independent of supply voltage...
Std cell gates usually have global nets for the supplies and you need them for
* LVS, or
* interfaces between analog & digital.
And interface handling depends on the tools you use and your technology/PDK - and why do you need them anyway? Do you have different digital supplies?
B.O.E