The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> VDD/VSS ESD protection issue
https://designers-guide.org/forum/YaBB.pl?num=1239795494

Message started by trashbox on Apr 15^th, 2009, 4:38am

Title: VDD/VSS ESD protection issue
Post by trashbox on Apr 15^th, 2009, 4:38am

Hi all,
As the attachment, the left-side is a general vdd/vss ESD protection circuit. How the M1/M2 works when it is under Positive-mode ESD test as described in the right-side? Thanks in advance!

--Trashbox

Title: Re: VDD/VSS ESD protection issue
Post by loose-electron on Apr 17^th, 2009, 10:41pm

Those types of circuits require a large signal failure mechanism called "punch through" giving conduction from drain to source even though the gate threshold has not been exceeded.