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https://designers-guide.org/forum/YaBB.pl Analog Verification >> Analog Functional Verification >> Co-simulation using synopsys tools https://designers-guide.org/forum/YaBB.pl?num=1239817251 Message started by Dracon on Apr 15th, 2009, 10:40am |
Title: Co-simulation using synopsys tools Post by Dracon on Apr 15th, 2009, 10:40am Dear All I have available Synopsys tools such as: HSPICE 2008.03 , VCS 7.0 , HSIMPLUS 2008.09 and NANOSIM 2005 . Does anybody have simple flow on how to proceed simple Co-simulation combining spice netlist, RTL code and verilog-AMS?? I've been trying a lot and doesn't figuered that out for now. Thanks a lot Dracon |
Title: Re: Co-simulation using synopsys tools Post by Mike Demler on Apr 15th, 2009, 6:28pm I can put you in touch with a CAE at Synopsys who can help you. Can you provide an email address? Regards, Mike Demler |
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