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Design >> RF Design >> Interstage matching techniques?
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Message started by drgz on Apr 15^th, 2009, 11:16am

Title: Interstage matching techniques?
Post by drgz on Apr 15^th, 2009, 11:16am

Hello,

I've searched a bit around on the forum, but I can't find the answer I'm looking for so I hope it's OK that I start a new topic.

As the topic name states, I'm searching for good interstage matching techniques.

At the moment I'm working on a two-stage MMIC pHEMT LNA for a school project. I got a working circuit which fulfills all the requirements (so I'm not asking anyone to do my homework ;)), but I think I can improve my circuit by doing some proper interstage matching.

I've tried some different approaches, but I'm not sure if I'm doing things 100% correct, so I thought maybe someone in here could give me some hints.

This is one of the approaches I've tried so far:

1. Find Bias-point for both stages
2. Match input of stage one to Z_Opt
3. Run SP simulations for stage one ONLY at f_c (with no match on the output), and write down S22 at f_c
4. Match output of stage two to Z_L
5. Run SP simulations for stage two ONLY at f_c (with no match on the input), and write down S11 at f_c
6. Match S22 (output of stage one) to S11 (input of stage two) with lumped components
7. Remove input matching network on stage one and output matching network on stage two, and then math to the new Z_Opt on the input of stage one, and conjugate load on output of stage two.

I'm not sure if this is correct at all or not, but for me it seems like one possible approach, although the results I get doesn't confirm that ::)

The other approaches basically builds on trying and failing in ADS, by just trying different matching networks for the interstage.

Any hints will be deeply appreciated :)

Best regards,

drgz

Title: Re: Interstage matching techniques?
Post by pancho_hideboo on Apr 21^st, 2009, 9:06am

I assume all DUT are linear.

Measure S-parameters and Gamma_Opt of stage-1(DUT_1). I set these as [S_DUT_1] and Gamma_Opt_1.
Measure S-parameters and Gamma_Opt of stage-2(DUT_2). I set these as [S_DUT_2] and Gamma_Opt_2.

Then connect two DUT using matching networks like following.
Gamma_S-[S_Match_In]-[S_DUT_1]-[S_Match_Mid]-[S_DUT_2]-[S_Match_Out]-Gamma_L

Here
Gamma_S is reflection coefficient of source.
Gamma_L is reflection coefficient of load.
[S_*] means two-port S-parameters.

[S_Match_In] can be determined by Gamma_S and Gamma_Opt_1 if noise matching is chosen for input.
[S_Match_Mid] can be determined by Gamma_S, [S_Match_In], [S_DUT_1] and Gamma_Opt_2 if noise matching is chosen for interstage.
[S_Match_Out] can be determined by Gamma_S, [S_Match_In], [S_DUT_1], [S_Match_Mid], [S_DUT_2] and Gamma_L.

If you choose power matching for interstage, easiest approach for interstage matching is introducing interface impedance, e.g. 50ohm, 100ohm, 500ohm, etc.
In this case, half of [S_Match_Mid] can be determined by Gamma_S, [S_Match_In], [S_DUT_1] and interface impedance value.
Another half of [S_Match_Mid] and [S_Match_Out] can be determined by interface impedance value, Gamma_L and [S_DUT_2].

But interstage matching by this latter method is redundant, here many matching components are required.
Generally inductor is used as output load for DUT_1.
We can also use this inductor as part of interstage matching, here there is no interface impedance concept.

I usually implement interstage matching as resonator or filter without introducing interface impedance, here both [S_Match_Mid] and [S_Match_Out] have to be tuned at same time.

Title: Re: Interstage matching techniques?
Post by drgz on Apr 21^st, 2009, 2:38pm

thanks a lot for your help! i will try it out this weekend and see if i can improve my results :)