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Design >> RF Design >> PLL layout optimization
https://designers-guide.org/forum/YaBB.pl?num=1239855340

Message started by aaron_do on Apr 15^th, 2009, 9:15pm

Title: PLL layout optimization
Post by aaron_do on Apr 15^th, 2009, 9:15pm

Hi all,

not really sure where to post this so sorry if it should be somewhere else. Just wondering is it okay to take all the digital blocks of a PLL (dividers charge pump etc) and place them underneath the loop-filter capacitance in order to save space?

Is it also safe to place other low-frequency analog blocks underneath (VGA, limiters etc)? Maybe i could add a ground plane in between...

thanks,
Aaron

Title: Re: PLL layout optimization
Post by ci on Apr 15^th, 2009, 11:00pm

Aaron,

You may consider providing more details about your design in order to get an adequate advice. For example, if your digital blocks of the PLL are differential the overall capacitive coupled signals will cancel out as common mode and you won’t have any problems. Also, if your filter cap is connected in single ended or differential configuration makes a difference. If single ended, one plate is AC ground (or at least it can be assumed to be) and you can use it as shield instead of adding an additional ground plane. Anyway, more details about your design may result in more specific advice.

Cosmin
NoiseCoupling.com
http://www.noisecoupling.com

Title: Re: PLL layout optimization
Post by aaron_do on Apr 15^th, 2009, 11:33pm

thanks for the reply,

the PLL wasn't actually designed by me, but i know that the digital blocks are not differential. The cap is connected in single-ended and I get your point about the ground plane - thanks. The reference frequency is 1 MHz and the VCO output is 2.4 GHz. The MIM caps use a metal 5 and metal 6 layer and my primary concern I guess is that either the signals from my digital blocks will couple to the loop-filter capacitor and modulate the VCO, or the the large ground plane will lower the frequency of operation of my circuits...

Is there any other specific info that would be helpful?

thanks,
Aaron

Title: Re: PLL layout optimization
Post by chenyan on Apr 16^th, 2009, 5:50am

Hi Aaron,

I think it is really risky to put divider and charge pump kind of circuits under your loop filter. Hard switching of these circuits generate very high AC currents as well as voltage on the supply (1MHz can not be effectively bypassed with reasonable size RC). The interferers coupled to loop filter modulate the VCO which can be converted to spurs. This is never a option for high performance pll.

Even if you add a ground plane. The groud plane is not perfect, the interfers still can be coupled to your loop filter. Of course, depends on the Kvco, and the application of your pll. The spur level might be acceptable. But I never dared to try that.

Title: Re: PLL layout optimization
Post by chenyan on Apr 16^th, 2009, 6:21am

Hi Cosmin,

I have some doubt about what you said about differential circuits. Even if differential circuits generate common mode harmonics which can not be cancelled when coupled.

Also as I said, the ground plate is never perfect. A single ended filter still couples.

Correct me if I was wrong.

cheers
chenyan

Title: Re: PLL layout optimization
Post by ci on Apr 18^th, 2009, 8:32pm

Hi Chenyan,

You are correct, the ground plate is never perfect and coupling from differential circuits does not completely cancel out. However, many other things if not all in our designs are not perfect and we need to live with them like this.

In a "good" conductive capacitor plate located above differential circuits, the inputs/outputs and differential signals couple capacitively equal magnitude and opposite phase signals, which of course if we assume negligible resistance and inductance in the plate cancel out. We know this is never the case, but we know that this cancellation phenomenon happens to some extent, not completely. Besides these differential signals differential circuits may couple transient switching signals, which are "single ended" and thus do not have equal magnitude and opposite phase cancellation signals. However, this coupling is much smaller than in the case of single ended CMOS logic.

So yes, some coupling still occurs from differential circuits and it will always happen through different mechanisms even if we do not place the MIM cap filter above circuits. The effects and impact of this coupling on performance needs to be evaluated on each specific case, and the necessary performance-cost tradeoff needs to be decided also in each specific design.

Regards,
Cosmin
NoiseCoupling.com
http://www.noisecoupling.com

Title: Re: PLL layout optimization
Post by mobil on May 13^th, 2009, 5:25am

Covering the transistor with the metal is really risky!!!
Reducing your CP output current and the value of capacitor might available to decrease for the same loop bandwidth.

Title: Re: PLL layout optimization
Post by Berti on May 13^th, 2009, 6:43am

Mobil, can you please elaborate why you think that covering transistors with metal is "really risky!!!"?

Most transistors are somehow covered with metal due to metal-density rules.

Cheers

Title: Re: PLL layout optimization
Post by rfmems on May 15^th, 2009, 12:13am

Berti wrote on May 13^th, 2009, 6:43am:

Mobil, can you please elaborate why you think that covering transistors with metal is "really risky!!!"?

Most transistors are somehow covered with metal due to metal-density rules.

Cheers

I think it is all about coupling which causes spurious tones and pulling for sensitive circuits. Usually metal filling can be excluded for these blocks.

Title: Re: PLL layout optimization
Post by loose-electron on May 16^th, 2009, 4:46pm

Personally I think its design suicide. Dumping a pile of active logic underneath the capacitor that controls the most noise sensitive node in a PLL?

Good luck with that. - Even if you put a metal grounded shield between them, I would still wager that you get some magnetic coupling.

Model the problem with some quantitative assumptions on noise coupling and see what happens.