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Design Languages >> Verilog-AMS >> how to write a verilogA code to generate a voltage source?
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Message started by liletian on Apr 16^th, 2009, 10:43am

Title: how to write a verilogA code to generate a voltage source?
Post by liletian on Apr 16^th, 2009, 10:43am

Hi Guys
Can anyone tell me how to generate a voltage source from some data(no analysis equations), I attached the voltage source in the pic, any suggestions will be appreciated. Also, any suggestions on how to design an amplifier to amplify the pic DC signal, I want to get digital output out of the curve.
Thanks

Title: Re: how to write a verilogA code to generate a voltage source?
Post by pancho_hideboo on Apr 17^th, 2009, 4:05am

liletian wrote on Apr 16^th, 2009, 10:43am:

Can anyone tell me how to generate a voltage source from some data(no analysis equations), I attached the voltage source in the pic, any suggestions will be appreciated.

If you use Cadence Spectre or Agilent GoldenGate, use "analogLib/vpwlf".
If you use Agilent ADS(RFDE), use "adsLib/VtDataset" or "adsLib/VtUserDef with adsLib/DataAccessComponent".

If you want to implement this source using Verilog-A, use $table_model() system function.
http://edocs.soco.agilent.com/display/ads2009/System+Tasks+and+IO+Functions

liletian wrote on Apr 16^th, 2009, 10:43am:

Also, any suggestions on how to design an amplifier to amplify the pic DC signal, I want to get digital output out of the curve.

Design comparator and use it as Data Slicer.

Title: Re: how to write a verilogA code to generate a voltage source?
Post by liletian on Apr 17^th, 2009, 9:20am

pancho_hideboo wrote on Apr 17^th, 2009, 4:05am:

liletian wrote on Apr 16^th, 2009, 10:43am:

Can anyone tell me how to generate a voltage source from some data(no analysis equations), I attached the voltage source in the pic, any suggestions will be appreciated.

Also, any suggestions on how to design an amplifier to amplify the pic DC signal, I want to get digital output out of the curve.

Design comparator and use it as Data Slicer.

Thanks a lot, I tried analogLib/vpwlf, it does works. I also tried Agilent ADS(RFDE), use "adsLib/VtDataset" or "adsLib/VtUserDef with adsLib/DataAccessComponent", but I did not figure out how to use it.if you do not mind, please explain more.
it will be greatly appreciated.
also, what is your mean of "Data Slicer", can you explain more?
Thank you

Title: Re: how to write a verilogA code to generate a voltage source?
Post by pancho_hideboo on Apr 17^th, 2009, 10:11am

liletian wrote on Apr 17^th, 2009, 9:20am:

I also tried Agilent ADS(RFDE), use "adsLib/VtDataset" or "adsLib/VtUserDef with adsLib/DataAccessComponent",
but I did not figure out how to use it.if you do not mind, please explain more.

In Agilent ADS(RFDE), you can't use "analogLib/vpwlf".
Instead you have to use "adsLib/VtDataset" or "adsLib/VtUserDef with adsLib/DataAccessComponent".

If you want to use "adsLib/VtDataset", dataset must be ADS's Dataset, that is, "*.ds" file which is binary.
In your case, Dataset is "osci_mixer_new_bak.ds". Expression is "OUT".

If you use "adsLib/VtUserDef with adsLib/DataAccessComponent", you can use ascii file as datafile which can be shared with "analogLib/vpwlf". Usually I use ascii file of Generic MDIF style for this purpose.

http://edocs.soco.agilent.com/display/ads2009/VtDataset+%28Voltage+Source%2C+Time+Domain+Waveform+Defined+in+Dataset%29

http://edocs.soco.agilent.com/display/ads2009/VtUserDef+%28Voltage+Source%2C+User-Defined%29
http://edocs.soco.agilent.com/display/ads2009/DataAccessComponent+%28Data+Access+Component%29

liletian wrote on Apr 17^th, 2009, 9:20am:

what is your mean of "Data Slicer", can you explain more?

See http://www.maxim-ic.com/appnotes.cfm?an_pk=3671

For $table_model() system function of Verilog-A, what error did you encounter ?
Did you specify $abstime as "table_inputs" of $table_model() ?

Title: Re: how to write a verilogA code to generate a voltage source?
Post by liletian on Apr 17^th, 2009, 1:24pm

pancho_hideboo wrote on Apr 17^th, 2009, 10:11am:

liletian wrote on Apr 17^th, 2009, 9:20am:

I also tried Agilent ADS(RFDE), use "adsLib/VtDataset" or "adsLib/VtUserDef with adsLib/DataAccessComponent",
but I did not figure out how to use it.if you do not mind, please explain more.

what is your mean of "Data Slicer", can you explain more?

See http://www.maxim-ic.com/appnotes.cfm?an_pk=3671

For $table_model() system function of Verilog-A, what error did you encounter ?
Did you specify $abstime as "table_inputs" of $table_model() ?

thank you so much, the verilogA code works now.

Title: Re: how to write a verilogA code to generate a voltage source?
Post by patrick on Apr 17^th, 2009, 5:36pm

Most simple use of $table_model to define a source, in this case a pulse:

`include "disciplines.vams"

module src(p,n);
electrical p,n;
analog V(p,n) <+ $table_model($abstime, {1,2,3,4,5}, {0,0,1,1,0}, "1CC");
endmodule

Time is used as the lookup variable with the (x,y) data defined using arrays (you'll probably use a file). On the control string, 1 => linear interpolation, "CC" - constant extrapolation both ends.

Patrick