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Design >> Analog Design >> delay circuit
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Message started by Ajay on Apr 20^th, 2009, 6:40am

Title: delay circuit
Post by Ajay on Apr 20^th, 2009, 6:40am

Hi all,

I need a circuit for introducing delay . Delay needed is a few microseconds . Can someone guide me ?

thanks

Title: Re: delay circuit
Post by buddypoor on Apr 20^th, 2009, 6:48am

Ajay wrote on Apr 20^th, 2009, 6:40am:

Hi all,

I need a circuit for introducing delay . Delay needed is a few microseconds . Can someone guide me ?
thanks

For one frequency only ? Or for a certain band ?
Did you consider already an allpass circuit ? It´s easy to realize.
Have a look into a textbook on filter theory/circuits.

Title: Re: delay circuit
Post by Ajay on Apr 21^st, 2009, 2:18am

Hello,
Its a digital signal that I need to delay.
When the input signal has a falling edge, the output of the delay circuit should go low after a few microseconds.
Can someone clarify how to implement this ?

Thanks.

Title: Re: delay circuit
Post by Berti on Apr 21^st, 2009, 3:13am

Do you have a clock available? Then you could implement a counter.

Cheers

Title: Re: delay circuit
Post by aamar on Apr 21^st, 2009, 7:53am

Two cascaded inverters will delay the signal without inverting it. If one of the inverters is larger than the other (alpha ratio>1) you can then control the delay.
Another possible way is to use a transmission gate as a resistance together with the input capacitance of the next gate will form an RC delay element

Best regards,

aamar

Title: Re: delay circuit
Post by thechopper on Apr 21^st, 2009, 9:46am

hi,
Apart from what aamar proposed, an additional option would be to have a couple of current-starved inverters. then the delay is controlled by such current and the input capacitance of the inverters.

Regards
Tosei

Title: Re: delay circuit
Post by jiesteve on Apr 21^st, 2009, 9:45pm

If you can build a current source, use it to generate a small current to discharge a large capacitor. Precharge the cap to VDD and start discharging when the signal flips. The delay can be trimmed by varying the discharge current, capacitor size and the trip point of the inverter that follows it.

Title: Re: delay circuit
Post by Peruzzi on Apr 22^nd, 2009, 7:45am

Ajay,

All the responses are viable choices, but a couple of very important criteria were left out of the original question: How precise does the delay have to be, and does it need to be consistent over processing, power supply voltage and temperature? Your answer to this determines which of the proposed solutions you choose.

Best regards,

Bob P.
www.RPeruzzi.com

Title: Re: delay circuit
Post by Ajay on Apr 25^th, 2009, 7:02am

Hello Peruzzi,

The delay circuit must give a delay of nearly 3us for all process corners and temperature variation from -40 to +125 degreeC. Supply voltage can vary from 1.8V to 3.6V.

Which solution is the suitable one ??

Thanks and regards.

Title: Re: delay circuit
Post by Peruzzi on Apr 25^th, 2009, 10:00am

Ajay,

Berti's solution wins, because of your requirement for consistant delay over PVT. Use digital delay -- a divided down clock and a counter.

Any other opinions?

Best regards,

Bob P.
www.RPeruzzi.com

Title: Re: delay circuit
Post by cmos.analogvala on Apr 25^th, 2009, 10:12am

This Clock + counter is a useful only if clock frequency doesn't vary with PVT. If I am not wrong, clock frequency varies with PVT.

CA

Title: Re: delay circuit
Post by Peruzzi on Apr 25^th, 2009, 10:23am

CA,

I suppose everything varies with PVT to some extent. ;)

Ajay hasn't posted all the constraints, but with a crystal oscillator and PLL, clock variance across PVT can be made negligible.

Bob P.
www.RPeruzzi.com