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Design Languages >> Verilog-AMS >> CUVDNF: Could not determine discipline
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Message started by makelo on Apr 20^th, 2009, 11:04pm

Title: CUVDNF: Could not determine discipline
Post by makelo on Apr 20^th, 2009, 11:04pm

I am having trouble in AMS Designer with the error:

ncelab: *E,CUVDNF (./ihnl/my_lib/my_cell/schematic/verilog.vams,123|30): Could not determine discipline for this expression .

In spectre, I run my my simulation consisting of a mixture of spectre and Veriloga files with no difficulties. However, when I switch the simulator to AMS, I get this error. I looked at one other thread, that hypothesized this error to occur with veriloga discipline voltage vs electrical, but the answer was inconclusive. I also seem to get it with other disciplines like logic.

I have tried changing the order of the hierarchy editor 'view list', and switched up the default connect rules, to no avail.

Does anyone have any guidance on how to avoid this error? Is it a connect rules issue?

Thanks,
Makelo

Title: Re: CUVDNF: Could not determine discipline
Post by boe on Apr 21^st, 2009, 2:47am

makelo wrote on Apr 20^th, 2009, 11:04pm:

Does anyone have any guidance on how to avoid this error? Is it a connect rules issue?

The simulator cannot determine whether a connect module is required or not. Did you try Cadence error help:
> nchelp ncelab CUVDNF

B.O.E.

Title: Re: CUVDNF: Could not determine discipline
Post by makelo on Apr 28^th, 2009, 4:38pm

The error goes away by changing all type Voltage I/Os to type Electrical.

Not the ideal fix, as I believe the type Electrical increases the information being tracked by the simulator which slows the simulation.

I have checked that the issue exists with both IUS6.2, IUS8.2 and with connect libs, ConnRules_5V_full, ConnRules_18_full. Are there other connect rules that should be used with type Voltage?

Title: Re: CUVDNF: Could not determine discipline
Post by Andrew Beckett on May 1^st, 2009, 5:29am

It sounds like you need to use the resolveto keyword in your connectrules:

Code:

connect electrical,voltage resolveto electrical;

This avoids changing the I/Os and will only impact nodes where you are connecting voltage to electrical disciplines.

In practice I don't think it makes much difference to the simulator...

Regards,

Andrew.