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Modeling >> Behavioral Models >> variable capacitor linked to an RC circuit
https://designers-guide.org/forum/YaBB.pl?num=1240593386

Message started by Seario on Apr 24^th, 2009, 10:16am

Title: variable capacitor linked to an RC circuit
Post by Seario on Apr 24^th, 2009, 10:16am

Hello guys...

I'm trying to implement a code where a variable capacitor is interconnected with a RC circuit in which the resistor is also variable... Yes it sounds quite bizarre and indeed it is. I've tried several things, but my lack of experience and time are killing me, so I claim for your feedback and help... When I try to run this code in smartspice it shows quite crazy results...

I'll appreciate if you can help me...

Cheers
Seario

My Verilog-A code is:

`include "discipline.h"
`include "constants.h"

module blue(p,n);
inout p,n;
electrical p,n,internal;

branch (internal,n) br_resist;
branch (p,internal) br_capvar;

parameter real V_rest = 7.0;
parameter real Vmax = 25.0;
parameter real V_pin = 17.0;
parameter real CC = 0.30281f from [0:inf);

real Vg;
real ITB;
real lock;
real lock1;
real flg;
real Eq1, Eq2, Eq3, Eq4, Eq5, Eq6;
real salida;
real salida1;

analog
begin

Vg = V(p,n);

if(abs(Vg) <= V_rest)
begin
lock = 0;
lock1 = 0;
end

if(Vg > 0)
flg = 0;
else
flg = 1;

if(Vg == Vmax)
begin
lock = 1;
end

if(Vg == -Vmax)
begin
lock1 = 1;
end

if((Vg < Vmax) && (lock != 1))
begin
lock = 0;
end

if((Vg >-Vmax) && (lock1 != 1))
begin
lock1 = 0;
end

if((Vg > 0) && (lock == 0))
begin
if((Vg >= 0) && (Vg < V_pin))
begin
Eq1 = 5.69e-15*exp(0.0123*V(br_capvar));
salida = Eq1;
end

if((Vg >= V_pin) && (Vg <= Vmax))
begin
Eq2 = 6.69e-15*exp(0.0299*V(br_capvar));
salida = Eq2;
ITB = 0.0068*exp(0.2583*V(br_resist));
salida1 = ITB;
end
end

if((flg == 0) && (lock == 1))
begin
if((Vg >= V_rest) && (Vg <= Vmax))
begin
Eq3 = 3.945e-15*exp(0.0507*V(br_capvar));
salida = Eq3;
ITB = 0.0068*exp(0.2583*V(br_resist));
salida1 = ITB;
end
end

if((Vg < 0) && (lock1 == 0))
begin
if((Vg <= 0) && (Vg > -V_pin))
begin
Eq4 = 5.69e-15*exp(-0.0123*V(br_capvar));
salida = Eq4;
end

if((Vg <= -V_pin) && (Vg >= -Vmax))
begin
Eq5 = 6.689e-15*exp(-0.0299*V(br_capvar));
salida = Eq5;
ITB = -0.0068*exp(-0.2583*V(br_resist));
salida1 = ITB;
end
end

if((flg == 1) && (lock1 == 1))
begin
if((Vg <= -V_rest) && (Vg >= -Vmax))
begin
Eq6 = 3.945e-15*exp(-0.0507*V(br_capvar));
salida = Eq6;
ITB = -0.0068*exp(-0.2583*V(br_resist));
salida1 = ITB;
end
end

I(br_capvar) <+ ddt(salida);
I(br_resist) <+ salida1 + CC*ddt(Vg) + I(br_capvar);

end
endmodule

Title: Re: variable capacitor linked to an RC circuit
Post by Ken Kundert on Apr 24^th, 2009, 3:04pm

I have not checked your model in detail, but I have the following comments:

You should start by reading the paper on modeling nonlinear capacitors: http://www.designers-guide.org/Modeling/varactors.pdf.

You should get rid of the equality tests on real numbers (Vg == Vmax), the chance of those ever being satisfied is negligible.

The fact that you add the capacitor current into the resistor is very unusual, and probably wrong.

You should also be careful about discontinuities, as they will cause convergence problems.

-Ken