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Design Languages >> Verilog-AMS >> Clock state
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Message started by nishant22 on Apr 26^th, 2009, 9:26am

Title: Clock state
Post by nishant22 on Apr 26^th, 2009, 9:26am

Hi I am writing Verilog A model for a block which has 2 clocks coming as inputs, both may have different frequency. I have to check if during the simulation any of the clock dissapears or is stopped, my output should go to zero. How can I model this? And it should detect that when both clocks come back again and execute rest of my model.
Its really important.
Thanks,
Nishant

Title: Re: Clock state
Post by Peruzzi on Apr 27^th, 2009, 8:30am

Hello Nishant,

You can devise an algorithm to do this. For each clock.

For each rising edge detection, find the difference between the present time and the time of the previous rising edge and the frequency is the reciprocal of that difference.

If the frequency is within tolerance, set some status variable indicating OK, and set up a timer() function to return execute some time in the future, corresponding to your definition of "if during the simulation any of the clock dissapears or is stopped".

Do a similar thing when the timer() executes to make sure the clock frequency is still OK. You have to mess around with it a little to get it right, but I'm sure this is enough to get you going.

You get the idea, right?

You can also google around for "loss of clock detection".

Bob P.
www.RPeruzzi.com