The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Simulators >> AMS Simulators >> Importing Verilog files in Virtuoso https://designers-guide.org/forum/YaBB.pl?num=1241082884 Message started by jefkat on Apr 30th, 2009, 2:14am

Title: Importing Verilog files in Virtuoso Post by jefkat on Apr 30th, 2009, 2:14am Hi, I imported a big hierarchical verilog design into cadence using 'Verilog In' from CIW. The problem is that the generated functional views dont have include statements anymore. As a result my ams simulator compains about the undefined constants.   How can I solve it? Thanks shaf

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