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Design >> Analog Design >> area efficient high resistance implementation
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Message started by manodipan on Apr 30th, 2009, 4:57am

Title: area efficient high resistance implementation
Post by manodipan on Apr 30th, 2009, 4:57am

Hi guys,
I want an area efficient very high resistance(~ 4-5 MOhms) ,also the resiatnce is required to be controllable as i am using this to control the current source......off transistors can implement high resistance but process variation effect is very high...so can you suggest some literatures on that.....thank you..

Title: Re: area efficient high resistance implementation
Post by Andrew Beckett on May 1st, 2009, 5:40am

I think this and your previous post are in the wrong forum, since they're design questions. Perhaps Ken can move them...

Regards,

Andrew.

Title: Re: area efficient high resistance implementation
Post by thechopper on May 7th, 2009, 7:17pm

Have you thought of using a MOS with long L in triode mode. There are a lot of techniques for controlling the on resistance of such device (for example to make it linear over a large dynamic range).

Regards
Tosei

Title: Re: area efficient high resistance implementation
Post by vivkr on May 10th, 2009, 11:35pm


manodipan wrote on Apr 30th, 2009, 4:57am:
Hi guys,
I want an area efficient very high resistance(~ 4-5 MOhms) ,also the resiatnce is required to be controllable as i am using this to control the current source......off transistors can implement high resistance but process variation effect is very high...so can you suggest some literatures on that.....thank you..


Hi,

No matter how you realize an on-chip resistance, the process variation will be quite high as long as there is no external precise reference available. You have to live with atleast +/- 20-30% variation in most cases. Else, you must consider trimming.

For realizing high resistance, you can use a narrow MOS transistor.

Regards,

Vivek

Title: Re: area efficient high resistance implementation
Post by ndnger on May 11th, 2009, 2:03am

Try to change your circuit architecture so that you can rely on the matching of identical MOS to cancel the variation, ie, circuit becomes ratio dependent.

Title: Re: area efficient high resistance implementation
Post by loose-electron on May 23rd, 2009, 2:41pm

if you are using the resistance to define a current source valuation (as sort of stated in your original post) you may want to consider geometry scaling or ratio driven design.

How about some more details on what you are trying to do? (you may not need that resistor at all)

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