The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> analysis type "static" not recognized
https://designers-guide.org/forum/YaBB.pl?num=1241597926

Message started by aaron_do on May 6^th, 2009, 1:18am

Title: analysis type "static" not recognized
Post by aaron_do on May 6^th, 2009, 1:18am

Hi all,

this was my first try on creating a verilog-a model. I wanted to create a switch which is on for dc operating point type analyses such as dc, pss and the dc operating points of ac, sp, noise etc.

The code I used is based on the code given by pancho_hideboo in a previous post. Anyway this is the code i used.

Quote:

`include "constants.vams"
`include "disciplines.vams"

module analysis_switch(vp,vn);
inout vp, vn;
electrical vp, vn;

analog begin
if( analysis("static"))
V(vp, vn) <+ 0.0;
else
I(vp,vn) <+ 0.0;
end // analog

endmodule

Unfortunately, the simulator doesn't seem to recognize the analysis type "static" as the switch is not closed when I use dc analysis. I wanted to double check so after a bit of experimenting i found that I could simply type in the CIW,

simulator('spectre)
analysis("static")

and it came up with the following message

Quote:

Invalid analysis type: static. Valid choices are tran(ac dc
noise xf sp spss pss pdisto spac spnoise spxf pac pnoise
pxf). Use ocnHelp('analysis) for more information.

So on inspection we can see that the analysis type "static" is not on the list. However, when i typed in analysis("ac") it gave me the exact same warming even though analysis type "ac" is on the list.

I'm totally lost here. Does anybody know how I can fix this. I need to either create the switch in another way, or fix the setup issue which seems to exist.

thanks,
Aaron

Title: Re: analysis type "static" not recognized
Post by Geoffrey_Coram on May 6^th, 2009, 7:23am

"static" has been in the LRM for years, so I'm pretty sure your simulator should support it. Note that the simulator itself doesn't have an analysis by that name, but the Verilog-A compiler/interpreter is supposed to understand "static" to mean dc, op-pt preceding ac, etc.

What version are you using? What did you use to test it? I put your module, a resistor, and a voltage source in series, and got the right answer.

Title: Re: analysis type "static" not recognized
Post by aaron_do on May 6^th, 2009, 7:36am

Hi,

thanks for the reply. Sorry i really don't pay too much attention to the inner workings of the software so i'm not too sure about all the answers.

So believe i'm using cadence version IC5141USR5. Is that the version you're asking about? So i assume the dc voltage was able to propagate through the switch right? It isn't working for me. Furthermore if I change line 9 to

if( analysis("dc", "static"))

it still doesn't work. Isn't the "," sign supposed to act as an OR function? Note that if I do

if(analysis("dc"))

then the switch works. However, that will not work for the operating point calculated in the ac analysis.

thanks,
Aaron

P.S. Is it possible that some component of the software hasn't been properly installed? If so where would I start looking? thanks!

Title: Re: analysis type "static" not recognized
Post by Geoffrey_Coram on May 6^th, 2009, 11:49am

spectre -W is the subversion info for the simulator, but the IC version is good enough to tell me that you're using a rather old version. On the other hand, we have a 5.10 version of Spectre, and it works for me. I don't think there's any installation problem that would cause this problem.

Yes, the comma is supposed to act as an OR. You could try
if (analysis("dc") || analysis("static") )

Did you try a very simple netlist?

Title: Re: analysis type "static" not recognized
Post by aaron_do on May 6^th, 2009, 6:38pm

Hi Geoffrey,

it is unable to work for a simple netlist. I used the same netlist as you did: a voltage source the analysis_switch and a resistor. The current does not flow through the switch for either ac or dc analysis. Seems to be unable to recognize the analysis type "static". My version of spectre is 6.1.1.133.

When I use
if (analysis("dc") || analysis("static") )
the analysis("dc") part works, but not the analysis("static").

thanks for the help,
Aaron

Title: Re: analysis type "static" not recognized
Post by Paul Floyd on May 7^th, 2009, 5:10am

Hi

The 2.3 LRM says that ac, dc, noise, tran, ic, static and nodeset should be supported, plus any other simulator-specific options.

Paul

Title: Re: analysis type "static" not recognized
Post by aaron_do on May 7^th, 2009, 5:28am

Hi Paul,

is there any way to confirm whether they are supported in my simulator? By the way what is the 2.3 LRM?

thanks,
Aaron

Title: Re: analysis type "static" not recognized
Post by Geoffrey_Coram on May 8^th, 2009, 7:00am

LRM means (Verilog-AMS) Language Reference Manual. The latest is 2.3. "static" has been in since at least 2.1, which is much older than your version of Spectre. I'd really be surprised if it is a simulator problem.

Title: Re: analysis type "static" not recognized
Post by aaron_do on May 8^th, 2009, 8:10am

Could it be a setup problem with the verilog simulator?

Title: Re: analysis type "static" not recognized
Post by Geoffrey_Coram on May 11^th, 2009, 7:55am

SourceLink solution number 1837470 says to use "static" ... for version 4.4.3.

Can you change versions at all -- either backwards or forwards? Can you send the test case to Cadence?

Title: Re: analysis type "static" not recognized
Post by Paul Floyd on May 12^th, 2009, 5:09am

aaron_do wrote on May 7^th, 2009, 5:28am:

Hi Paul,

is there any way to confirm whether they are supported in my simulator? By the way what is the 2.3 LRM?

thanks,
Aaron

Hi

It depends on the simulator I guess. Mentor Graphic's [my employer] ADVance MS will print a warning at compile time if the string is not one of the recognized ones.

Paul

Title: Re: analysis type "static" not recognized
Post by aaron_do on May 12^th, 2009, 11:45pm

Quote:

Can you change versions at all -- either backwards or forwards?

Thanks for all the help guys. I managed to get the code working by switching to MMSIM621 from MMSIM611. Not sure why that worked but anyway...

Aaron

Title: Re: analysis type "static" not recognized
Post by Andrew Beckett on May 29^th, 2009, 12:53am

I'm wondering where you're testing this. In the very first post you talked about typing:

analysis("static")

in the CIW. Well, that's not Verilog-A that's SKILL (or OCEAN). So the analysis function there is for setting up an analysis in an OCEAN script. There's no such analysis as "static" so it's hardly surprising that doesn't work.

I dont' know why analysis("static") wouldn't work in a VerilogA model in spectre; this has been supported for as long as I can remember.

Andrew

Title: Re: analysis type "static" not recognized
Post by aaron_do on May 29^th, 2009, 1:55am

Hi Andrew,

I guess my experimenting by typing into the CIW was not correct. I'm not at all familiar with SKILL (or OCEAN) so I can't really comment on your point. Either way the cell was not working. I was told that there are some bugs in our version of MMSIM611. When I switched to MMSIM621 the cell worked.

btw I actually wanted to learn some basics about SKILL or OCEAN just to get an idea of what it is. Do you know any useful resources?

thanks,
Aaron

Title: Re: analysis type "static" not recognized
Post by Andrew Beckett on Jul 10^th, 2009, 7:05am

The best thing for OCEAN is to attend a Cadence OCEAN training class (OK, I'm biased, because I wrote the class).

But otherwise you could look at the OCEAN Reference in the installation:

<ICinstDir>/doc/oceanref/oceanref.pdf

And also the SKILL Language User Guide:

<ICinstDir>/doc/sklanguser/sklanguser.pdf

Or use cdsdoc (or cdnshelp if using IC61) to read these documents.

Regards,

Andrew.